Implementation of JPEG Static Image Compression Algorithm Based on DSP Builder

Abstract: Using the digital signal processing development tool DSP Builder provided by Altera and modern DSP technology, a JPEG algorithm model was established in the Matlab/Simulink environment, and simulation verification was carried out. Finally, the compiled code was downloaded to the hardware for online debugging.
Keywords: DSP Builder; JPEG; image compression; FPGA

With the rapid development of digital signal processing technology in the application field, the traditional DSP technology with DSP processors (such as TI's TMS320 series) as the core device of the application system is difficult to meet the user's requirements for the reconfigurability or customizability of the DSP system due to its immutable hardware structure and fixed data bus width. The emergence of modern DSP technology with large-capacity and high-speed FPGA as the core device has successfully solved the above problems. FPGA is embedded with configurable high-speed RAM, PLL, hardware multiplier and accumulator and other DSP modules. Therefore, using FPGA to implement digital signal processing can well solve the problems of parallelism and speed, and its flexible configurable characteristics make the DSP system with FPGA as the core device easy to modify, test and upgrade hardware.
This paper uses DSP Builder, a system-level design tool for DSP development launched by Altera. Based on an in-depth study of the principles of the JPEG algorithm, it designs a JPEG algorithm model and performs algorithm-level simulation in the Matala/Simulink environment. Finally, the algorithm is compiled and downloaded to the FPGA hardware. Using the HIL (Hardware In Loop) function of DSP Builder, Simulink inputs test data to the hardware through a download cable, and then sends the test results to Simulink for display. This method achieves hardware-level simulation verification.
1 Introduction to DSP Builder
DSP Builder development tool is a digital signal processing platform provided by Altera. It is a system-level (or algorithm-level) design tool that is built on multiple software tools and connects the design tools in the two design fields of system level and RTL level, maximizing the advantages of the two tools. DSP Builder relies on Matlab/Simulink, a mathematical analysis tool from MathWorks, and appears as Simulink's Blockset. Graphical design and simulation can be performed in Simulink. At the same time, the design files (.mdl) of Matlab/Simulink can be converted into corresponding hardware description language VHDL design files (.vhd) and TCL scripts for controlling synthesis and compilation through Signal Compiler. The latter can be processed by Quartus II, a FPGA/CPLD development tool.
Designers can design multiple HDL models or QuartusII software design projects at the same time, generate an independent simulation model for each module, and simulate HDL modules with standard Simulink/DSP Builder models in the same design environment. In addition, the tool can make full use of and reuse existing designs, thereby greatly improving product development speed. In terms of simulation software, in addition to using Simulink's simulation environment, DSP Builder also provides an interface with Modelsim to fully utilize the advantages of Modelsim simulation. In the past, DSP developers could only directly use VHDL or VerilogHDL language to design FPGA DSP systems, which was quite difficult. Now, using the FPGA-based DSP development tool DSP Builder and a complete software development platform, designers can follow a development method similar to the software design process to carry out FPGA DSP design, greatly improving the design efficiency. The system-level development process based on DSP Builder is shown in Figure 1.

2 JPEG Algorithm Principle

The JPEG expert group developed two basic compression algorithms, one is a lossy compression algorithm based on discrete cosine transform (DCT); the other is a lossless compression algorithm based on prediction technology. When using a lossy compression algorithm, when the compression ratio is 25:1, it is difficult for non-image experts to find the difference between the compressed and restored images and the original images, so it has been widely used. For example, in VCD and DVD-Video television image compression technology, the JPEG lossy compression algorithm is used to eliminate redundant data in the spatial direction.
JPEG compression is lossy compression, which utilizes the characteristics of the human eye's visual system and uses a combination of quantization and lossless compression coding to remove redundant information of the visual angle and redundant information of the data itself. The JPEG algorithm block diagram is shown in Figure 2.

Compression coding can be roughly divided into three steps:
(1) Use forward discrete cosine transform (FDCT) to transform the image represented in the spatial domain into an image represented in the frequency domain.
(2) Use a weighting function to quantize the DCT coefficients, which is optimal for the human visual system.
(3) Use the Huffman variable word length encoder to encode the quantized coefficients. The decoding (or decompression) process is the opposite of the compression coding process.
3 Implementation of the JPEG algorithm model
The system is built under DSP Builder. The DSP Builder platform provides adders, multipliers, and many modules involved in digital signal processing, and these modules can be visually edited. This design imports the image to be compressed from Matlab's Workspace, and then compresses and decodes it through the JPEG compression algorithm built with DSP Builder, and finally displays the reconstructed image in Matlab. The JPEG static image compression algorithm compresses the object in YCbCr format, so preprocessing is required before image compression. The RGB format image is converted into YCbCr format through Color Space Conversion in Matlab.
The image data to be compressed must first undergo DCT transformation. Due to the limitation of FPGA hardware resources, a one-dimensional row transformation can be performed first, and the obtained data can be stored in RAM by column. After all the data is input into RAM, a one-dimensional DCT row transformation is performed on the data in RAM. Then the one-dimensional DCT module is reused to save hardware resources.
The frequency coefficients after DCT transformation must be quantized. The JPEG algorithm uses a uniform quantizer for quantization, and the quantization step size is determined according to the location of the coefficient and the hue value of each color component. Because the human eye has different sensitivities to brightness signals and color difference signals, two quantization tables are used. The design implementation method is: divide the DCT coefficient by the quantization step size and take an integer. In order to ensure that the low-frequency component appears first and the high-frequency component appears later in the DCT coefficient, the quantized coefficients must be rearranged. The JPEG algorithm uses Z-shaped encoding, which increases the number of consecutive "0" coefficients, that is, the run length of "0", so as to achieve the purpose of using less data to represent more information, thereby optimizing the encoding. The purpose of quantization is to reduce the amplitude of non-"0" coefficients and increase the number of "0" value coefficients.
The JPEG algorithm uses the differential pulse modulation coding (DPCM) technique to encode the difference (Delta) of the quantized DC coefficients between adjacent image blocks. The quantized AC coefficients are characterized by many "0" coefficients in the 1×64 vector, and many "0"s are continuous, so they are encoded using a very simple and intuitive run length encoding (RLE). Entropy coding can also be used to further compress the DC coefficients encoded by DPCM and the AC coefficients encoded by RLE. In the JPEG lossy compression algorithm, entropy is reduced by using the Huffman encoder because the Huffman encoder can be encoded using a very simple lookup table method. When compressing data symbols, the Huffman encoder assigns shorter codes to symbols with higher frequency and longer codes to symbols with lower frequency. This variable-length Huffman code table can be defined in advance.
The last step of JPEG encoding is to combine various marker codes and the encoded image data into frames of data for easy transmission, storage and decoder decoding. This data is usually called JPEG bit data stream.
4 Model Simulation Analysis
The design is simulated and verified using DSP Builder's HIL. HIL wraps the design in a set of interfaces for compilation and then downloads it to the FPGA of the board. First, the model file (.mdl) is compiled using SignalCompiler to generate a Quartus II project file (.qpf); then the project file is loaded into the HIL module, and the clock, reset and other signal settings are performed in the HIL module, and the FPGA device model is selected; finally, the file is compiled and the configuration is downloaded to the FPGA. Simulink continuously inputs the test data through the download cable, and then continuously obtains the results of the hardware operation at the output end. Using HIL to simulate on hardware can speed up the simulation speed, and at the same time, the algorithm, timing and pin configuration can be tested. Since FPGA can be burned unlimited times, it is very convenient to use HIL for simulation. The HIL simulation module is shown in Figure 3.

Using HIL to simulate and verify the compression and decompression of images, it can be found that the simulation model successfully implements the encoding and decoding algorithm of JPEG static image compression, and the decompressed image has a good effect. The Quartus II project file (.qpf) compiled by SignalCompiler is downloaded to the FPGA chip. It is observed that the number of logic unit blocks LE (Logic Elements) used is 1,224, while the JPEG algorithm written in VHDL language will occupy 1,483 unit blocks when downloaded to the FPGA chip. Table 1 shows that using DSP Builder for system-level algorithm design saves more hardware resources than using traditional VHDL language for design.

Applying modern DSP technology, a JPEG static image compression codec model was built through the digital signal processing development tool DSP Builder provided by Altera, and the HIL simulation was used for verification. The experimental results show that the designed JPEG model can successfully realize the compression codec of static images, and the reconstructed image effect is very good. Using DSP Builder for system-level algorithm design saves more hardware resources than using VHDL language design.