Simulation and Implementation of Pulse Compression Based on FPGA

1 Introduction

With the development of modern weapons and aerospace technology, radars are required to have high precision, long distance, high resolution and other performance. Simple rectangular pulse radars have a contradiction between radar detection capability and distance resolution. To solve this contradiction, most modern radars use pulse compression technology to modulate the signal frequency or phase, thereby generating a large bandwidth signal. The receiving end receives it through a receiver with a matched filter to generate a narrow time pulse and improve the distance resolution. Pulse compression implemented in a digital way has high reliability, good flexibility, programmability and easy application. Therefore, a distributed algorithm is introduced here to implement time domain pulse compression. It is a calculation method based on a lookup table. The partial products generated by each corresponding bit of each input data are pre-added to form the corresponding partial products, and then the partial products are accumulated to form the final result, thereby realizing the multiplication and addition function. Compared with the traditional algorithm (all products are generated and then added to complete the multiplication and addition operation), the distributed algorithm can greatly reduce the scale of hardware circuits, facilitate pipeline processing, and improve the execution speed of the circuit.

2 Pulse Compression

2.1 Pulse Compression Processing Process

Pulse compression processing has two methods: time domain and frequency domain. Among them. Time domain processing is a process implemented by digital finite impulse response (FIR), that is, the convolution of the signal and the coefficient; while frequency domain processing is to first use FFT to calculate the spectrum S(ω) of the digital echo signal, then multiply it by the frequency response H(ω) of the matched filter, and finally perform inverse fast Fourier transform (IFFT) to obtain the pulse compression result. Generally speaking, for large time-width bandwidth signals, frequency domain processing is better; for small time-width bandwidth signals, time domain processing is better. The implementation methods of pulse compression signals are: linear frequency modulation signal, nonlinear frequency modulation signal and phase coded signal. Linear frequency modulation signal obtains a large time-width bandwidth product through nonlinear phase modulation or linear frequency modulation (LFM). Compared with other pulse compression signals, it has the advantage that the matched filter is insensitive to the Doppler shift of the echo signal. The LFM signal used here is processed by a matched filter and has a signal with different Doppler shifts.

The IFM digital pulse compression simulation process includes linear frequency modulation (LFM) signal generation, echo signal simulation, orthogonal coherent detection, I/O two-way signal low-pass filtering and extraction, and video signal (zero intermediate frequency) matched filtering, as shown in Figure 1. The matched filter, as a key part, is a linear phase FIR filter, and its filter coefficient is the complex conjugate of the transmitted signal, h(n)=x*(Nn), and in order to reduce the side lobe, the coefficient is generally given a corresponding weight.

2.2 Pulse compression processing simulation

Assume that the carrier frequency of the linear frequency modulation signal is fo=25 MHz, the modulation frequency bandwidth is B=5MHz, the sampling frequency is fs=20 MHz, the requirements of the intermediate frequency sampling theorem are met, the pulse width is τ=60μs, the target distance is 12 km, the time delay pulse repetition period is 320μs, and the signal amplitude is A=l. The number of sampling points of a pulse is L=Tfs=1 200, and the time bandwidth

product of the linear frequency modulation signal, that is, the pulse width compression ratio is D=300, then the output pulse width is r\'=60μs／300=200 ns. The target echo signal of the linear frequency modulation signal generated by the above parameters is extracted by the I/Q two-way signal generated by orthogonal coherent detection. Finally, the MATLAB simulation of each process of matched filtering is carried out, and the pulse compression result is shown in Figure 2. As can be seen from Figure 2, a narrow pulse is generated after pulse compression, and the output waveform has the properties of the Singer function. In addition to the main lobe. There is also a series of extended side lobes on the time axis. In addition, it can be seen that. After Hamming weighting, the first sidelobe is about 40 dB lower than the main lobe, and the width of the main lobe is also expanded accordingly, which is much better than the result of unweighted pulse compression.

3 Logic Design and Simulation

3.1 Hardware Structure of Distributed Algorithm

Based on the principle of distributed algorithm, the hardware structure of distributed algorithm implemented by FPGA is obtained, as shown in Figure 3.

In Figure 3, N is the filter order of the module, so the DALUT has 2N storage units. If the number of filter taps is too large, the size of the lookup table increases exponentially with the increase in the number of taps. Therefore, when implementing a high-order filter, the lookup table must be divided. Because the convolution operation is linear, the total output can be obtained by adding the output of each sub-table. The logic design is based on Altera's Stratix series FPGA platform, and the logic design is performed using VHDL language and schematics in OuartusII software. [page]

3.2 Design of 5th-order FIR filter

The LPM_ROM module of the Stratix device has at least 32 (25) storage units, so the filter module order N is set to 5. The design of the 5th-order filter module is shown in Figure 4, where lpm_dff0 is a 12-bit latch, 5 latches shift and register the input data, firda5 is a distributed algorithm module, and the DATAS[11:0] output pin is the last latch output of the filter module, which is used as the data shift between different filter modules when the filter modules are cascaded.

The distributed algorithm module firda5 realizes data parallel-to-serial conversion, DALUT table lookup, and weighted accumulation. The state machine is used in the design to realize the state transfer of the distributed algorithm, which simplifies the calculation process and plays a key role in realizing the algorithm. According to the state transfer relationship of the distributed algorithm, each time a data is input, before the next data is input, it is necessary to stay in state s1 for the clock time of 12-bit data width and 2 register clock times (in QuartusII software, the device uses the Stratix series, uses the LPM_ROM module, the address input is the register input, and the data output also includes the register) and a data output clock time: Therefore, the system clock must be 16 times the data clock. The div 16 in the figure realizes 16 division.

3.3 Design of 50-order matched filter

Since the matched filter is a finite impulse response (FIR) filter with linear characteristics, a high-order filter can be realized by directly cascading and adding low-order filters. The shifted data DATAS[11:0] of the previous filter is used as the signal input of the next filter module. Each filter module is designed according to Figure 4, and only the data in the DALUT table needs to be changed according to different coefficients. The logic design of the 50th order matched filter is shown in Figure 5. The Imatch50 module is a 50th order filter corresponding to the real part of the complex coefficients of the matched filter, and the Qmatch50 module is a 50th order filter corresponding to the imaginary part of the complex coefficients of the matched filter. The output signal includes a 16-bit I signal and a 16-bit O signal.

For the waveform simulation of the matched filter, the input data is the 12-bit data simulated by MATLAB. Since the filter performs a 50x50 point convolution, the output data is 50+50-1=99. The simulation waveform is shown in Figure 6.

4 Conclusions

The whole design is verified by simulation analysis of the pulse compression process and tuning test. It can be seen that the use of distributed algorithms can greatly reduce the amount of digital pulse compression operations and improve the efficiency of pulse compression. Since the coefficients of the matched filter are symmetrical with the center and point, the linear phase FIR filter can be used in the FPGA implementation algorithm, so that the filter design with the same performance can reduce the hardware scale by half. At the same time, convolution can also be achieved by time-division multiplexing of embedded multipliers, which will save more logic units and have the ability to realize more functions.