DSP and FPGA Implementation of HDLC

HDLC (High-Level Data Link Control) is widely used in the field of data communication and is an important technology to ensure reliable intercommunication of data information. The general method of implementing HDLC is usually to use ASIC devices or software programming.

HDLC ASIC chips are easy to use, have strong targeted functions, and reliable performance, making them suitable for mass production of products for specific purposes. However, due to the large number of texts in the HDLC standard, ASIC chips are difficult to be used in different versions for the purpose of specialization, and lack application flexibility. Some chip companies also have their own standards, with different regulations for the CRC (cyclic redundancy check) sequence generator polynomial of HDLC. The ASIC chip dedicated to HDLC has limited on-chip data storage capacity, and usually only a few bytes of FIFO (first-in-first-out memory) are available. For some applications, when it is necessary to expand the capacity of the data cache, the ASIC can only be connected to an external memory or other circuit, and the simplicity and ease of use of the ASIC is offset. The software programming method of HDLC is flexible and can be applied to different HDLC applications by modifying the program. However, the program operation occupies a lot of processor resources, the execution speed is slow, and the delay and synchronization of the signal are difficult to predict. Pure software HDLC can generally only be used for low-speed signal processing of individual channels.

FPGA uses hardware technology to process signals and can be repeatedly programmed through software. It can take into account both speed and flexibility, and can process multiple signals in parallel. Its real-time performance can be predicted and simulated.

DSP uses software technology to process signals and can be programmed and used repeatedly. Although the cost of DSP and FPGA chips is slightly higher than that of ASIC chips, they have the advantages of smooth supply and can be programmed and used multiple times. In the design and production of small and medium-volume communication products, using FPGA and DSP to implement HDLC functions is a method worth adopting.

HDLC frame structure and CRC check

In order to enable the FPGA design to implement the basic functions of HDLC and flexibly adopt different CRC check algorithms in accordance with the provisions of various standards, we first look at the basic frame structure of HDLC.

HDLC is a bit-oriented link control protocol. Its link monitoring function is implemented through commands and responses represented by certain bit combinations. These monitoring bits and information bits are transmitted together in the form of frames. The following is the basic frame structure of HDLC specified in the ISO/IEC 3309 standard.

Other HDLC standards also have similar frame structures. The start and end of each frame are marked by "7E" (01111110), and between two "7E"s are the data segment (including address data, control data, information data) and the frame check sequence. The frame check uses the CRC algorithm to check all data except the inserted "zero". In order to avoid mistaking the "7E" in the data as a flag, the data stream and frame check sequence should be "inserted zero" and "deleted zero" at the sending and receiving ends.

Realizing HDLC Function Using FPGA+DSP

The "Top to Down" method is generally used for functional design of FPGA devices, that is, first design the top-level principle block diagram according to the required functions, which is usually composed of several functional modules. Then each module is refined into sub-modules. For more complex designs, each sub-module can be divided into layers of lower-level sub-modules. The functions of each layer can be implemented using hardware description language or circuit diagrams.

The design of DSP is based on the method of software sequential execution. The main function calls the sub-function, and the sub-function can also be divided into lower-level sub-functions. The current DSP design software is mainly completed in C language.

The HDLC protocol operation is completed by FPGA and DSP together: HDLC receiving end: First, FPGA receives the data, then judges the frame header "7E" and the local address. If it is data sent to the local machine, the subsequent data is judged. If there are 5 consecutive "1"s and the next data bit is "0", the next "0" is deleted. After deleting zeros, the data is stored in FIFO. When the frame tail "7E" is received, the receiving end flag is given; then the DSP reads the receiving end flag. If the flag is "1", the FIFO is read empty, the flag is cleared, and the data content is subjected to CRC check.

HDLC sending end: First, DSP writes the data into FPGA's FIFO, and then gives a flag. After receiving the flag, FPGA first sends the frame header "7E", and then sends the data. If there are 5 consecutive "1"s in the data, a "0" is inserted after it. After the data is sent, the frame tail "7E" is sent.

FPGA Design

The link layer protocol implemented in FPGA is mainly used to complete the transmission and reception of HDLC data interface and complete the data interaction with DSP. The circuit consists of three parts: interface module inteRFace, HDLC data sending module transmitter and HDLC data receiving module receiver.

FPGA interface module interface

The main function of the interface module is to enable DSP to read and write parallel data to FPGA through data and address buses and read and write signals.

In this example, the width of the data bus depends on the data bit of the DSP used. Since most DSP processors are 64-bit or 32-bit, and 8 bits are enough to complete data exchange, the 8-bit data bus cpu_data[7..0] is used here. The address bus includes the register address of the decoded selection send FIFO and receive FIFO, the command register and the status register.

For DSP, FPGA can be regarded as an ordinary chip. Through chip select CS/, read and write signals RD/ and WR/, FPGA can be selected and read and write operations can be performed on it.

When FPGA needs to pass information to DSP, the interrupt signal output terminal interrupt/ becomes low level. After DSP responds, it can read the detailed interrupt information from the status register in FPGA and make corresponding processing.

FPGA data transmission module HDLC_Send

The main functions of the HDLC_Send module are: generating the internal data transmission clock tx_clk for HDLC; latching the transmission data written by DSP into FIFO and starting the transmission according to the specified timing; adding a "7E" start mark before the transmission data segment; performing a "zero insertion" operation on the transmitted data and CRC calculation results and attaching a "7E" end mark to output the results (see Figure 1).

The txhdlc module consists of a data sending submodule, a mark data zero insertion submodule, and a "7E" sending module.

The data transmission clock tx_clk of HDLC is obtained by dividing the external input clock and can perform internal operations at a speed higher than the bit transmission speed.