Design of FIR digital filter using CPLD

At present, the requirements for real-time and fast digital signal processing are getting higher and higher, both in military and civilian fields. As programmable logic devices (PLDs) are rapidly increasing in speed and integration, more and more electronic systems use programmable logic devices to implement digital filtering.

Altera's FLEX10K is the first embedded PLD in the industry, with advantages such as high density, low cost and low power. The main structural feature of the device is that in addition to the main logic array block (LAB), the embedded array block (EAB) is used for the first time. Each array block contains 8 logic elements (LE) and a local interconnect. An LE is composed of a four-input lookup table (LUT), a programmable register and a dedicated signal channel for carrying and cascading functions.

In the FLEX10K device, each group of logic elements (8 LEs) is composed of a logic array block (LAB), and all logic array blocks (LABs) are arranged in rows and columns. A single EAB is also included in a row. Multiple LABs and multiple EABs are connected to each other using fast channels. The

embedded array block (EAB) is an important component in the structural design of the FLEX10K series devices. It is a flexible RAM block with registers for both input and output ports. The size and flexibility of the embedded array block (EAB) are suitable for more memory. Functions include multipliers, vector standards and error correction circuits. In applications, these functions can be combined to complete the functions of digital filters and microcontrollers.

The programmable embedded array block (EAB) with a read-only platform can perform logical functions during configuration and establish a large lookup table (LUT). In this lookup table, the combinational logic function is performed with the results of the lookup without calculating them. Obviously, the execution of this combinational logic function is faster than the usual algorithm execution in logic, and the dedicated EAB is easy to apply and quickly provides possible predictable delays. This article

introduces the method of using Altera's FLEX10K series CPLD to quickly complete convolution to realize the design of finite impulse response ( FIR ) filters. Table lookup method to realize convolution operation method The basic structure of the finite impulse response (FIR) filter is a segmented delay line. The output of each segment is weighted and accumulated to obtain the output of the filter. Mathematically expressed as:

The structure is shown in Figure 1. It consists of weighted summing of tapped signals on a delay line with evenly spaced taps.

According to the above formula, it can be seen that FIR digital filter involves a large number of convolution operations, which will take up a lot of resources when implemented using conventional hardware. By making full use of the table lookup structure of the FLEX10K series chip, the convolution operation is converted into a table lookup shift sum to achieve it. For example: for the formula

y = [x(1) h(1)] + [x(2) h(2)] + [x(3) h(3)] + [x(4) h(4)] (1)

Assume that x and h are both unsigned binary integers with a width of two digits and two values ​​as follows:

h(1) = 01, h(2) = 11, h(3) = 10, h(4) = 11

x(1) = 11, x(2) = 00, x(3) = 10, x(4) = 01

From Figure 2, we can see the implementation of the operation of formula (1). The four data in the intermediate data p1(n) are actually the result of multiplying the lowest bit of the multiplier x(n) by h(n), and the value is either 0 or h(n). Further consideration is that the values ​​of the intermediate data p1 and p2, that is, "100" and "011", are composed of the sum of different h(n), and the choice of h(n) is determined by the same bit of the multiplier x(n). For example, if the lowest bit of x(n) in the above figure is 1001, then the value of p1 is h(1) + h(4); if its high bit is 1010, then the value of p1 is h (1) + h(3). Therefore, by using the lookup table (LUT) structure in Altera's FLEX device, various combinations of h(n) are stored in the lookup table in advance, and the convolution operation in the above example that originally required 4 multiplications and 3 additions is converted into 1 addition. Figure 3 shows the structure of implementing this example using a lookup table.

When using the lookup table method to implement convolution operations, there are two structures: parallel and serial. Figure 3 shows a parallel structure, in which the two LUTs are exactly the same. In the parallel structure, the number of LUTs is determined by the data width of x(n). One bit corresponds to one LUT, so that the speed is maximized. In the FLEX10K structure, two dedicated data channels are provided, namely the carry chain and the cascade chain. Through the cascade chain, adjacent LUTs can be used to calculate various parts of the function in parallel.

Using the FLEX10K chip to implement the FIR digital filter

The FELEX10K series chip has a lookup table structure, which is used to implement the FIR digital filter using global parallelism, that is, the input x(n) is processed simultaneously after different delays.

The hierarchical structure diagram of the FIR digital filter is shown in Figure 4:

The controller module (contr) generates control signals to control the delay, parallel-to-serial conversion, tap coefficient, and shift-addition modules so that they can be combined in a certain form to realize the filter function. After receiving the A/D conversion end signal, the controller module generates various control signals such as the shift register enable signal, the parallel-to-serial conversion load signal, the shift-addition load signal, the addition and subtraction control signal, and the filter result output signal in sequence, so that the above modules can operate according to a certain timing sequence, thereby completing the filtering function. The delay link module (shift-reg) is used to make the data after A/D conversion pass through different triggers, thereby generating different delays. The parallel/serial conversion module (ps-ff) is used to convert the different delays generated by the delay module into the serial address of the lookup table at the same time, and provide it to the tap coefficient module. The tap coefficient module (sub-rom) solidifies various combinations of tap coefficients in the ROM. Its address input receives the serial output of the parallel/serial conversion module, and then looks up the table to obtain the intermediate data of the convolution. The shift-addition module realizes the function of multiplying two numbers by shifting and adding the intermediate data.