Analysis of key technologies in automotive display interface design

According to IMS Research, the number of car head units with video capabilities will grow from 8.5 million in 2006 to 26.6 million in 2015. To provide information to the driver without distracting the driver, the display needs to be mounted away from the head unit and projected onto the back of the windshield. This video interface, which combines the image source and the panel, is increasingly moving from analog video technology to the higher quality RGB (red, green, and blue) digital video format that has become the standard interface used in LCD displays. Cable lengths for front-end display applications are typically kept in the 1 to 3 meter range, while cables for rear seat entertainment (RSE) units need to reach 8 meters or more. This connection supports data rates of Gigabits per second, far exceeding the baud rates of traditional in-vehicle networks, and can be perfectly implemented using point-to-point serializer/deserializer (SerDes) solutions. Compared with transmitting a wider parallel video bus, this chipset greatly reduces the number of transmission lines and connector pins, thereby achieving outstanding system-level advantages.

To meet the stringent requirements of automotive display interfaces, such as high data throughput, ultra-thin wiring, advanced signal conditioning, detectability, and ultra-low EMI (electromagnetic interference), National Semiconductor (NS) has developed the DS90UR905/6 and DS90UR907/8 SerDes chipsets, which are embedded clock SerDes solutions that can expand resolution from QVGA (400 x 240) to XGA (1024 x 768) with 24-bit color depth. The wide range of pixel clock frequencies allows automakers to use only one digital video display interface solution across their entire vehicle series, covering applications ranging from small dual-screen instrument panel panels, LCDs in center consoles to larger RSE displays.

Video Applications and SerDes Concepts

The target application area for SerDes components is the flat panel display link interface, which can connect the image host to the display through a long serial cable. Typical examples include: central information display (CID), instrument panel, entertainment display on the headrest or roof drop-down display module for rear seat passengers, as shown in Figure 1. These new chipsets are a group of products in the "FPD-Link II" series launched by NS. They can convert the 27-bit digital RGB color information and time control signals of a video source into a single serial data stream with embedded clock information for transmission on twisted pair. The chipset uses high-speed differential signaling at the I/O (input/output) level, that is, while the actual signal is transmitted on the "true" (positive) terminal, the corresponding opposite polarity signal is transmitted on the "complementary" (negative) terminal.

Figure 2 depicts the concept of video transmission at a system level. In addition to the color and timing bits, there is an optional I2C control interface that replaces the component configuration achieved through the conventional pin-striping options. The chipset supports color depths of 18bpp (bits per pixel) or 24bpp. Color displays use 3 sub-pixels (red, green, and blue) to define a single pixel. With 18 bits per pixel (6 bits of red, 6 bits of green, and 6 bits of blue), we can get 262,000 colors. Most people's eyes can see more than 10 million colors, which explains why the use of 24bpp has become a trend: it provides more than 16 million colors, allowing a richer user experience and smooth color gradients. The pixel clock range is now extremely wide: the frequency can be from 5MHz to 65MHz, which allows the serial link rate to increase from 140Mbps to 1.82Gbps, covering all mainstream resolutions of automotive displays.

Parallel LVCMOS input and output signals can be flexibly aligned to the rising or falling edge of the synchronous transmitter input and receiver recovered output clock (PCLK), respectively. This feature greatly simplifies the interface connection from the serializer to the image controller and the deserializer to the LCD timing controller. Within a certain frequency band around the transmitter parallel clock, the SerDes chipset does not require an external reference clock (quartz or oscillator) when "pre-synchronizing" the receiver's PLL. This synchronization can be guaranteed even during the transmission of all possible random data patterns, which is called the "random data lock" feature. This not only saves the cost of the reference component system, but also eliminates another potential source of electromagnetic interference. This performance also enables "hot plugging", that is, the serial data stream sent to the deserializer can be asserted/deasserted without any special sequencing or training mode.

Once the receiver PLL is locked to the transmitter frequency, this status is indicated by the LOCK output flag pin, ensuring the data integrity of the receiver output. The DS90UR907/8 chipset has all the features of the DS90UR905/6 chipset, except that the input and output are no longer parallel buses that send LVCMOS signals, but follow the open industrial standard "FPD-Link". Many modern image controllers, display timing controllers, ASICs and FPGAs support this "one-level serialization" technology, which uses 3 data channels for 18bpp or 4 data channels for 24bpp, each with a parallel clock channel. The transmission of electrical signals follows the open ANSI/TIA/EIA-644A standard, which is also called "LVDS" (Low Voltage Differential Signaling). The advantage of using this interface technology instead of conventional LVCMOS is that the use of differential signals can reduce electromagnetic interference and reduce the number of pins of components, as shown in Figure 3.

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Figure 3 Advantages of the FPD-Link system interface option

FPD-Link II Payload

During each pixel clock cycle, 28 "sub-symbols" are time-division multiplexed on the differential I/O into a serial data stream. The embedded payload contains 24 color bits, 3 timing signals (horizontal sync - HS, vertical sync - VS, and data enable - DE), and overhead bits. The interconnect line rate is 28x the pixel clock. At 65MHz, this rate translates to 1.82Gbps. The serial data stream is qualified by the "CLK1" HIGH bit at the front and the "CLK0" LOW bit at the end, which allows for smooth transitions between high and low levels between each frame, allowing the serializer's PLL to synchronize with it and extract the embedded clock information. Two overhead bits ("DCA" and "DCB" bits) are located in the middle of each frame, which include timing signals embedded in the transition process of the DCA and DCB bits. The payload bits are randomized, balanced, and scrambled to reduce harmonic electromagnetic interference and improve signal quality, and are DC balanced for AC coupling.

Since the longer the cable connection, the more likely it is that the ground potential will drift between the transmitter and receiver modules, the AC-coupled interface scheme can achieve potential decoupling by using series capacitors in the transmission line. The DC-balanced encoder in the serializer and the corresponding DC-balanced decoder in the deserializer can achieve a uniform distribution between high and low bits on the serial link to prevent ISI (inter-symbol interference) effects and blocking of static modes caused by capacitors. By configuring capacitors at both ends, this scheme can also provide input/output short-circuit protection when the cable is damaged or shorted to the ground or the net voltage on the board. Randomization and irregularity not only ensure good eye opening, but also minimize electromagnetic interference on the interconnection line. Overall, its coding efficiency is higher than 85%.

Enhanced signal conditioning capabilities

Signal conditioning technology plays a vital role in promoting long-distance high-speed connections. The signal restoration feature is used on the serializer side. Figure 4 is an example of a signal restoration operation. This series of transition bits, 0, 1, 000 and 1 in sequence, shows the single-ended (SE) waveform at the top of the figure, which can be measured relative to ground potential at the true value and output terminals. The differential (DIFF) signal is shown at the bottom of the figure, which is equivalent to the differential voltage swing at the input of the receiver within its terminal range. For the first transition, the first signal sent is a 0, forming a full differential swing. The next transition is a 1, also with a full voltage swing. Next is a series of 0s in time frames C, D and E, where the first 0 is the full voltage swing. With the arrival of the second and third 0s in time slots D and E, the amplitude will decrease, indicating that it has been "restored" by the signal. Therefore, the static charge in the cable will be limited, otherwise it will increase over time. This allows the final 1 sent in time slot F to form a full differential swing again. The signal restoration feature usually balances the internal energy of high and low frequency signals in the transmission line. The overall effect is a clean opening of the signal eye, with a single bit transition following a long sequence of 1s or 0s. The signal restoration layer is programmable to adjust to the optimum compensation level for the specific cable medium.

In addition, the signal restoration feature has a good effect in terms of adjustable differential output voltage (Vod), that is, it can double the differential output voltage (Vod) for long cable transmission. Signal restoration can achieve signal recovery without significantly reducing the signal amplitude at the receiver input. The input of the deserializer integrates a cable equalizer. When regenerating the entire signal waveform, this function is equivalent to a high-pass filter relative to the input signal, which can partially eliminate the low-pass filter effect caused by the transmission medium. The equalizer has programmable gain between 1.5dB and 12dB. Of course, all enhanced signal processing features can also be used in coordination to establish sufficient eye opening for error-free data recovery in long cable transmission.

Spread Spectrum Clock

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The deserializer is enhanced with an integrated configurable spread spectrum clock (SSC) generator. At the receiver output bus side, this causes the output clock frequency and data spectrum to vary slightly over time at a low modulation rate of tens of kHz. As shown in Figure 5, the frequency variation can occur around the nominal pixel clock center frequency ("center spread modulation"), or towards lower frequencies ("downward spread modulation"). The spectrum spread percentage can be as high as ±2%. Spread spectrum clocking spreads the peak energy over a wider spectrum range, greatly reducing the EMI noise level. Instead of switching all outputs at a constant frequency at the same point in time, where the radiated noise is concentrated in a narrow frequency band, all output data is synchronized with the output clock, which effectively spreads the data and clock. In particular, the DS90UR906 receiver output has a low voltage (LV) CMOS interface option that can greatly reduce electromagnetic radiation.

Enhanced diagnostic capabilities

Another feature is the built-in self-test (BIST) function. In this mode, the transmitter sends a pseudo-random bit sequence (PRBS). The receiver generates the same sequence internally and compares it with the received bit pattern. The user can control the duration of the BIST to find the best compromise between the overall test time and the minimum bit error rate that needs to be verified. The PASS pin is toggled in a clocked manner when an erroneous payload is encountered. The PASS pin stores the final result of the BERT (bit error rate test). If the test fails, one or more payload errors have occurred; if the test passes, the PRBS sequence was propagated and received without errors. At the far end of the link, the BIST does not require any data generator, data logging or measurement system. Car manufacturers can use the BIST mode to test the system and check the link operation. It can also be used as a test bench during the system development phase, sending data to the entire link without a video source, while applying a clock signal only on the transmitter. During the service or troubleshooting phase, the system test can be used to verify that the link is working properly to isolate the problem on the host or display side. Finally, when the car is started, the display interface can be routinely checked and connectivity verified.

More Enhancements

Further enhancements include integrated termination resistors, which reduce the complexity of board design, resulting in lower costs and less board space. A terminal common-mode filter pin is provided at the input of the deserializer. It is recommended that users ground the common-mode pin through a capacitor to ensure stability and to ensure that the common-mode voltage is filtered out of the frequency. This will reduce the level of electromagnetic radiation to the outside world and improve immunity to external noise sources. The immunity of digital video links to external interference is usually studied through large current injection (BCI) testing, using an inductor to modulate a side current of up to 300mA onto the cable shield. The I/O library is powered by VDDIO, either 1.8V or 3.3V. Such flexibility can take advantage of low interface levels and provide compatibility with downstream devices.

Generally speaking, when operating components at 1.8V, the level of electromagnetic interference is also reduced. In the case of power failure, the output voltage state of the deserializer can be set to tri-state (high impedance) or low impedance. The pixel clock (PCLK) state can also be set to tri-state or low impedance to select to stop the internal oscillator. In the latter case, the clock output will always exist regardless of whether there is an input signal. When the interface is only connected to a short-distance lightly loaded bus, the receiver drive strength (RDS) feature can minimize the current consumption of the output bus, slow down the output edge conversion rate and ultimately reduce electromagnetic interference. The chipset supports an ultra-wide temperature range of -40℃ to +105℃, which can be applied to various automotive electronic systems in different working environments. These chipsets are packaged in LLP, occupy a small space, and have passed RoHS certification and AEC-Q100 Grade 2 standard for comprehensive automotive application certification.

Conclusion

The new DS90UR905/6 and DS90UR907/8 FPD-Link II chipsets offer many system benefits and enhancements. Parallel video buses are serialized into a single group with an embedded clock, which reduces system cost, eliminates clock/data skew issues, reduces noise, and extends the link to long cable distances. The chipsets support all common automotive LCD resolutions from QWVGA to XGA with 24-bit color depth. To facilitate system design, qualification and approval, designers can focus more on features that reduce EMI. This minimizes the cost of protection requirements without sacrificing reliability. Diagnostic BIST modes facilitate factory testing and field applications, and are also beneficial for troubleshooting testing and diagnostics. As the third generation chipset in the FPD-Link II family, its components are based on a proven and trusted IP protocol and are backward compatible with previous generations of chipsets. The FPD-Link II chipset family represents a true plug-and-play solution optimized for the automotive industry as it does not compromise performance when used with low-density wiring, and offers high bandwidth, low power consumption, low EMI, ruggedness, and autonomous link synchronization.