Ambarella Semiconductor Liu Qingtao: Ambarella’s ADAS/autonomous driving solutions embrace the new era of smart driving

On December 16, the "2022 Smart Car Technology and Business Innovation Forum" in the Heart of the Car was successfully held. With the theme of "New Technology and New Business", it focused on car intelligence and gathered academic leaders and industry leaders in the smart car industry and autonomous driving industry chain. Big names, entrepreneurs, and investment tycoons attended the meeting and shared their views on the era of smart cars and the technological and business innovation opportunities in automotive technology. Through layer-by-layer analysis and trend judgment, we explored the future of China’s smart car innovation era.

At the conference, Liu Qingtao, general manager of Ambarella Semiconductor Technology (Shanghai) Co., Ltd. Shenzhen Branch, delivered a speech with the theme of "Ambarella ADAS/autonomous driving solutions, embracing the new era of smart driving", expressing his views on Ambarella's role in automotive intelligence. Solutions and technical advantages in the driving field were shared.

The following is a transcript of the speech, compiled by AutoHeart:

Hello everyone, my name is Liu Qingtao.

I am very happy to come and meet you at the Smart Car Technology and Business Innovation Forum hosted by Autoheart. The title I want to share with you today is "Ambarella ADAS/autonomous driving solutions, embracing the new era of smart driving".

01. Ambarella’s layout and technical advantages in the field of automotive intelligent driving

Founded in 2004, Ambarella is an AI vision chip company focusing on areas such as high-definition video image processing, AI computer vision, and autonomous vehicle driving.

In 2007, the Ambarella China team was established and successively set up R&D centers in Shanghai and Shenzhen.

In 2012, Ambarella was listed on Nasdaq.

In 2015, Ambarella acquired VisLab, a well-known autonomous driving company in the industry.

In 2021, it acquired  Aoku, a 4D millimeter wave radar algorithm company. In the same year, Ambarella accumulated mass production of more than 300 million high-definition camera chips.

In 2022, Ambarella released the high-computing power autonomous driving domain control SoC series CV3-AD.

Ambarella has branches all over the world, including America, Europe, and Asia. Ambarella's R&D team is mainly located in three places: Silicon Valley in California, the United States, Shanghai and Shenzhen in mainland China, and Hsinchu in Taiwan.

There are more than 200 people in the Shanghai and Shenzhen teams, focusing on China's local automobile market, and more than 85% of them are R&D technicians.

Ambarella has been working hard in the field of smart automotive electronics for many years. Let me introduce to you the Ambarella CV series of car-grade chips.

First of all, let’s do some popular science. The CV series chips mentioned here all have embedded computer vision processing engines, which are often called CVflow® AI hardware acceleration units.

CV series chips can be widely used in intelligent driving products that require AI intelligent algorithms.

According to different manufacturing processes, Ambarella CV series chips are mainly divided into two parts:

One is a 10-nanometer automotive-grade chip series: CV2FS, CV22FS, CV2AQ, CV22AQ, CV25AQ, CV28AQ (hereinafter referred to as "CV2x"). All series are based on the 10-nanometer automotive-grade process. All chips have been obtained in passenger car projects. Mass production, while the SDK software is compatible with each other and supports the development and optimization of multiple algorithms.

The CV2x series of chips provides Panshi comprehensive information security solutions, supports hardware information security, and has been mass-produced in multiple projects. In addition, among the CV2x series chips, CV2FS/CV22FS have reached the chip-level ASIL-C level and the functional safety island ASIL-D level.

The other is a car-grade chip series using 5nm advanced process:

今年安霸刚刚发布了 CV3-AD 大算力域控 SoC，后续还会发布 CV7x 系列的芯片。这两个系列芯片都支持硬件的 HSM，能够显著改善信息安全。同时 CV3-AD 系列芯片支持 ASIL-D 的功能安全岛，整个芯片可以达到 ASIL-B 功能安全等级。

Here is the chip grade ASIL-C certificate officially certified by EXIDA. In addition to the chip meeting functional safety requirements, the SDK software also meets the requirements of MISRA-C and ISO26262. If the customer's project requires functional safety, we can provide a complete functional safety manual and related technical documents.

The following focuses on the technical advantages of Ambarella chips. Before that, let’s review the pain points we often encounter during the development of intelligent driving:

The first major pain point is the artificially high chip performance. The AI ​​performance of the chip is very good on paper, but in actual application, it will encounter various performance bottlenecks, and the actual AI performance will drop sharply compared to the indicators in the specification. To describe it in one sentence, it means that it sounds invincible but in practice it is weak.

The second biggest pain point is that the power consumption of the chip remains high. The high power consumption of the chip not only increases the difficulty of development, but also lengthens the research and development cycle. If you are not careful, the chip and the entire project will become a hot potato.

The third major pain point is the unsatisfactory image quality. As a smart driving eye , the camera cannot clearly see the noise on the road.

The fourth pain point is that the AI ​​algorithm tool chain is not easy to use, often resulting in half the effort with half the effort.

The fifth point is that there is no effective technical support from the original chip manufacturer.

Ambarella's five major technical advantages can solve all these five major pain points. Let’s learn about these five technical advantages of Ambarella one by one.

Advantage 1: Ambarella chips have very strong AI performance and overall performance.

In the face of all kinds of dazzling marketing promotions in the market, Ambarella has worked hard to practice its internal skills and firmly believes that chip performance evaluation should be "seeing the efficacy without watching advertisements". In actual application scenarios, real AI performance is the most important.

Ambarella has always followed an algorithm-first strategy in chip development, testing and evaluating hundreds of open source networks and Ambarella's self-developed autonomous driving algorithms.

Not only evaluate existing mainstream neural networks, but also consider the development direction of future algorithms in advance.

The overall chip design is built around the core requirement of maximizing the performance of the algorithm in actual application scenarios.

Therefore, Ambarella's chip architecture takes into account both real-time performance and reliability. Traditional algorithms and deep learning algorithms are coordinated with each other. Each hardware module performs its own duties and collaborates efficiently. It runs as a whole to avoid seizing resources from each other and causing performance bottlenecks. Disadvantages, the overall performance of the chip is very excellent.

Based on the above design concepts, CV series chips naturally have super performance in actual application scenarios.

For example, in a comparison test of computing power between CV2AQ with a computing power of 12 eTops and a friend's GPU with a computing power of 30T, running the same algorithm, the AI ​​performance is equivalent, but the power consumption of CV2AQ is only 1/5 of the other.

At the same time, because the CV series chip is designed based on an algorithm-first strategy, it has very good compatibility with all AI algorithms and its performance is also very balanced.

The reason why Ambarella's CVflow® has such excellent performance comes from its specially designed chip architecture, which uses a variety of optimized data paths for heterogeneous computing.

Each data path corresponds to a special underlying hardware operator. We have many underlying operators, such as some used for general vector calculations, some used for tensor calculations, and some special calculations related to CV.

The upper-layer algorithm can very flexibly call or even combine these operators to achieve hardware acceleration of neural networks.

CVflow®'s unique hardware architecture design has rapidly improved its DRAM bandwidth efficiency. High performance, low latency and low power consumption are the distinctive features of Ambarella CV series chips.

Advantage 2: CV series chips have ultra-low power consumption.

This is because Ambarella not only has advanced 10nm or even 5nm semiconductor process technology, but also has first-class hardware architecture design, so it can have industry-leading AI performance and power consumption ratio.

Taking the CV2x series of chips as an example, the power consumption of CV28AQ can be less than 1. 5 watts. Even the CV2 AQ chip with the strongest AI computing power consumes less than 4 watts.

Compared with the hardware solutions of competitors that require air cooling or even water cooling for heat dissipation design, CV2 can complete the heat dissipation design using only simple heat sinks .

The various advantages brought by the low power consumption of the chip are obvious. It can save the development cycle, reduce the difficulty of development, and truly save developers time, effort, and worry.

At the same time, low power consumption can also eliminate various hidden dangers caused by heat accumulation. The system can operate safely even if it works for a long time in high temperature weather. At the same time, low power consumption can effectively reduce power supply costs, simplify heat dissipation design, and save the entire BOM cost.

In addition, another major advantage is that it facilitates function expansion and upgrade. For example, depending on the implementation scenario, high-specification chips can be used to replace mid- to low-specification chips in the same series based on the same hardware.