FlexRay has begun to show its strength in automotive electronic applications for single-channel high-speed power transmission, driver assistance and comfort enhancement. In the new BMW X5 car, FlexRay is used in suspension control, so that engineers and developers can have a gradual learning process to adapt and reduce the related risks before using this fault-tolerant deterministic protocol in safe driving functions using dual communication channels and bus monitoring.
In the development process of FlexRay applications, design engineers can build a robust network topology through five basic steps.
Step 1: The number of nodes and their assumed locations on the vehicle chassis must first be defined, and then the required cable length can be determined to implement a passive bus without stubs (a topology known as a “daisy chain”) where the bus ends at the cable terminations, as shown in Figure 1. If the cable length is less than 10 meters, the topology is complete and is considered ready for series production.
Step 2: Once you find that the cable length is greater than 10 meters, you should consider using an “active star” topology (see Figure 2). If the cable length exceeds 20 meters, an active star must be introduced. The simplest active star has only two branches, which divides the wiring harness into two electrically decoupled components. Because the active star can be enhanced with NXP’s TJA1080 transceiver (the first of its kind for the BMW X5), the total number of transceivers required only increases by one.
Step 3: If the application can continue to work after a vehicle crash, the system's collision-sensitive nodes should be distributed on different branches (see Figure 3). In this way, once the cable is squeezed or clamped on a differential voltage, only the data transmission of the affected branch will be interrupted, but the active star will ensure that the communication of other branches in the network is not affected.
Figure 1
Figure 2
Figure 3
Step 4: Due to the occurrence of resonance, nodes or wiring exposed to very harsh RF fields should also be distributed to different branches (see Figure 4). Using a ? ? terminal (FlexRay Electrical Physical Layer Specification v2.1 Revision B) at each end of the cable, the RF induced current is transferred to the ground position. This makes the common mode voltage amplitude on the cable lower while not affecting the nodes connected to other branches. Therefore, the jitter in the received data stream can be controlled within a reasonable range.
Figure 4
Step 5: To ensure that there are always proper (??) terminations at both ends of the cable (see Figure 5), the end nodes of the trunk cable should not be optional nodes. The electrical position of the node should not be moved along the cable in such a way that the cable length exceeds 10 meters. At non-optional nodes, short stubs (<1 meter) may be introduced. Even for greater flexibility, the active star does not have to be at the end of the cable.
Figure 5
Verification and optimization
Following these five steps will help to build a FlexRay topology that is robust in terms of electrical characteristics. It is recommended to perform simulations to further verify and optimize the defined topology. Monte-Carlo simulations are used to estimate manufacturing tolerances such as wiring harnesses, production ranges, and temperature dependence of transceivers and active star.
In addition, the FlexRay Alliance has introduced a complex and complete cable model that covers the skin effect of the wiring harness. While supporting car manufacturers in introducing FlexRay, NXP is also constantly improving its expertise in FlexRay topology simulation.
More information on terminals, cables and connectors for FlexRay applications can be found in the FlexRay Electrical Physical Layer Specification v2.1 Revision B. The Electrical Physical Layer Application Note v2.1 Revision B gives some recommendations for topology design. Both specifications are available on the FlexRay Alliance website. Technical details on the TJA1080 FlexRay transceiver can be found on the NXP website.
Following these recommendations will help reduce power consumption in system designs using FPGAs.
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