Implementation of single power supply ECG detection module based on ARM core

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The design given in this article uses a single power supply, which can solve the above problems and reduce product costs. At the same time, the design also uses a simple and practical algorithm in an embedded system based on the arm core, which can quickly and accurately locate the QRS complex (that is, calculate the human heart rate). The design is designed for a large number of home users, with a small size. It only needs a personal computer to connect to it to operate and observe the ECG signal in real time.

The basic architecture of the ECG signal acquisition system is shown in Figure 1. The ECG signal of the human body is sent to the system through electrodes and dedicated lead wires. Through filtering and amplification adjustment circuits, the weak ECG signal is amplified to a suitable amplitude and is within the A/D conversion range.

Basic architecture of ECG signal acquisition system

Figure 1: Basic architecture of the ECG signal acquisition system.

The control and data processing of the system are completed by the MCU ADuC7020 based on the arm7 TDMI core of ADI. This chip has a rich on-chip peripheral circuit, a processing speed of up to 40MIPS, and an A/D conversion speed of up to 1MSPS, which has a high cost performance. Finally, the results are sent to the computer through the UART port by ADuC7020, and the computer displays or stores the results intuitively through the interface written by LabVIEW. Figure 2 is the basic hardware circuit diagram.

Basic hardware circuit

Figure 2: Basic hardware circuit.

The amplitude of the ECG signal collected from the human body or the ECG signal generator is between 0.05 and 5 mV (usually 2 mV), and the frequency is between 0.05 Hz and 75 Hz. The ECG signal must pass through several circuits such as buffering, matching resistor network, voltage amplification and filtering.

The ECG signal first passes through a two-stage RC low-pass filter circuit and enters the buffer stage. Before the signal enters the system, the high-frequency component needs to be removed, so a low-pass filter with a cutoff frequency of 300Hz is designed here to ensure that the weak ECG signal of 0.05-75Hz will not be attenuated. The buffer stage is composed of a voltage follower, which can increase the input impedance of the entire amplifier circuit and reduce the output impedance. To ensure the consistency of the differential signal, an amplifier integrated on the chip should be selected. The matching resistor network usually uses the Wilson electric center terminal network, which obtains the Wilson electric center terminal as the reference point of the entire ECG system through a specific resistor network. [page]

The front stage of the filter amplifier circuit adopts a negative feedback differential amplifier circuit. Here, the instrument amplifier AD8221 with adjustable gain and high common mode rejection ratio from ADI is used as the front stage amplifier. The amplification factor is set to 8 times, which is calculated by the formula G=49.4kΩ/RG+1, where RG is the resistance value between the two RG pins of AD8221.

This resistor should be a high-precision, low-temperature drift metal film resistor to ensure the low noise performance of AD8221. The REF pin of AD8221 is not grounded, but forms a negative feedback loop with a low-pass filter to effectively filter out the DC component, so that the voltage at U1 is always clamped at 1.25V. Because it is powered by a single power supply, and the voltage of the ECG signal of different leads is positive and negative, a suitable clamping voltage must be provided. The voltage input range of ADuC7020 in AD conversion mode is 0-2.5V, and the middle value of 1.25V is selected as the clamping voltage here.

The single-ended signal amplitude output by AD8221 is very small, and there is a lot of interference mixed in it, so data processing is impossible. The post-filter amplifier circuit consists of an active low-pass with a large gain, and the gain is adjustable. The strength of the ECG signal of different people is different. Considering the attenuation, the gain is generally set to 150 times. The transfer function of the system is:

formula

Both low-pass filters are required to have low voltage offset, low temperature drift and low noise characteristics. ADI's rail-to-rail input and output dual op amp AD8607 can meet these requirements well. Since the second-stage amplifier is input at the inverting end, the final signal is inverted, which can be processed in software.

From the perspective of protecting patients and improving the common-mode rejection ratio of the system, the common-mode signal must be inverted and amplified before being fed back to the human body. In this way, the system and the human body together form a voltage parallel negative feedback network, which is commonly known as the right leg drive circuit. The processed ECG signal is converted by ADuC7020 and the ADC sampling mode controlled by the timer is selected. After an A/D conversion is completed, the ADC interrupt is triggered, and the digital signal is processed in the interrupt service program.

The processing of ECG digital signals is to accurately identify the QRS complex in the ECG signal. The width of the QRS complex of a normal person is 0.06 to 0.10 seconds and is not affected by changes in heart rhythm. In view of the sharp characteristics of the R wave, we use a key sliding time window to determine whether the signal peak and valley meet the requirements, and at the same time confirm whether it is within the time window. The double variable threshold method is used for the threshold of the signal amplitude, that is, the peak threshold and the valley threshold are set for the waveform. If the peak threshold and the valley threshold change significantly within a suitable period of time, the peak threshold and the valley threshold are reset. Next, we will discuss the positioning of the QRS complex and the calculation of the heart rhythm. Only the inversion and filtering processing are performed on the signal for a period of time at the beginning, in order to restore the inverted ECG signal and avoid the initial fluctuation of the signal affecting the threshold. Then, within a certain period of time, the peak threshold Thpeak and the valley threshold THtrough are set according to the sampled data, and then the QRS wave is located. Finally, the data is processed according to the following steps (see Figure 3).

Basic steps in data processing

Figure 3: Basic steps in data processing.

Read the new sampling point Ni:

1) Determine whether the amplitude of the sampled signal point is greater than the peak threshold Thpeak. If not, return to step 1).

2) If the condition is met, start counting n=1 and record the value of n as peaktime1. Slide the start edge of the time window to here.

3) Continue sampling Ni+1, and each sampling is n+1.

4) Determine whether the new sampling point Ni+1 is less than the valley threshold. If not, return to step 4).

5) If the sampling point is less than the valley threshold Thtrough, the n value of the point is recorded as troughtime1.

6. Determine whether the difference between the two signal point times troughtime1 and peaktime1 that meet the amplitude requirements is within the time window, that is, whether it is less than the window width THtime. If it is not less than THtime, return to step 1).

7) If it is satisfied, the signal is considered to be a QRS complex and Peaktime1 is positioned as an R wave.

With the located R wave, you can calculate the heart rate based on the following steps:

1) Find the first R wave and record the value of n as peaktime1;

2) Find the second R wave and record the n value as peaktime2;

3) Calculate the heart rate according to the following formula.

formula

Practice has proved that the heart rhythm calculated by this algorithm has high accuracy, simple calculation and easy implementation, and finally the ECG signal waveform and heart rhythm value can be observed on a PC.

Reference address:Implementation of single power supply ECG detection module based on ARM core

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