CAN bus application based on AVR processor at90can128

1 Introduction

Fieldbus is the most active field in the current industrial bus field, and CAN bus is one of the important fieldbuses in the industrial data bus field. CAN is the abbreviation of Control Area Network, which is an internationally standardized serial communication protocol. In today's automotive industry, various electronic control systems have been developed for the requirements of safety, comfort, convenience, low pollution and low cost. Since the data types used for communication between these systems and the requirements for reliability are different, there are many cases where multiple buses are used, and the number of wiring harnesses also increases. In order to reduce the number of wiring harnesses and communicate large amounts of data at high speed through multiple LANs, the German electrical company Bosch developed the CAN communication protocol for automobiles in 1986. Today, CAN is the standard protocol for automotive networks in Europe. The original intention of CAN was to solve the communication of various complex data in automobiles, and later it was proven that it can be used freely in many industrial fields.

2 CAN bus characteristics and current status

The difference between CAN bus and other communication networks is that: the target address is not included in the message transmission, based on the whole network broadcast, each receiving station filters the message according to the identifier reflecting the nature of the data in the message; it strengthens the focus on data security and meets the higher data requirements of the control system. It has the following significant features: extremely high bus utilization, low cost, high data transmission rate, long-distance transmission, reliable error handling and error detection mechanism, can decide to receive or block the message according to the message ID, the node has the function of automatically exiting the bus in the case of serious errors, etc.

The perfect communication protocol required by the CAN bus can be realized by the CAN controller chip and the interface chip, which greatly reduces the difficulty of system development, the cost of composition, and shortens the development cycle. Its high performance, high reliability, and flexible design have attracted people's attention and are increasingly widely used. Currently, the more popular controller chip is Philips' SJA1000 and transceiver chip TJA1050.

As CAN bus technology has been gradually promoted in my country in recent years, the unique characteristics of CAN bus technology, such as the reliability and real-time transmission of data, have been recognized in the field of international automation control, and its application prospects are very bright. The application cases that promote the advancement of CAN bus technology in China are constantly expanding, which has actively promoted the advancement of automation technology in my country. Due to the characteristics of CAN bus itself, its application scope has been expanded to process industry, machinery industry, CNC machine tools, medical machinery, household appliances and sensors, etc. In the elevator control system, the main board needs to receive multiple signals such as elevator calls from different floors, elevator calls in the car, and adjustment of elevator operating parameters, so the advantages of CAN bus are obvious. As shown in Figure 1.

Figure 1 CAN bus application topology

3 ARM microprocessor with integrated CAN controller

The CAN bus is based on a set of strict protocols, and is generally implemented by connecting a dedicated CAN controller to the main CPU. Due to the rapid development of microprocessors in recent years, many powerful CPUs with integrated CAN controllers have emerged, making the application of CAN bus easier. In terms of price, the price of microprocessors with integrated CAN bus is comparable to that of general processors plus dedicated CAN controller chips, so microprocessors with integrated CAN bus will inevitably become the trend of CAN bus applications in the future. The ARM structure LPC2294 produced by NXP is one of the popular CPUs with CAN bus controllers. It is based on a 32-bit ARM7TDM I-S CPU microcontroller that supports real-time simulation and tracing, and has 256k bytes of embedded high-speed Flash memory. Extremely low power consumption, multiple 32-bit timers, 8-channel 10-bit ADC, 4-channel CAN and up to 9 external interrupts make them particularly suitable for industrial control. Therefore, LPC2294 can also be used as the main controller of elevator control systems.

4 High-end 8-bit AVR with integrated CAN controller

As mentioned above, the elevator control system needs to process multiple information channels, and they may have different transmission rates, so CAN bus controllers with different channels are needed. For the control system, it must be operable. Considering the need to reduce the burden on the main CPU, a simple operating system is designed to operate the main system, and the data exchange method is to use CAN bus transmission. This operating system is called the secondary system in this article. The secondary system is relatively simple, and its functions mainly include: ! Exchange information with the main board; ? Have buttons for input; # Have a display for displaying information. In view of the functional needs and the size of the program, the 8-bit AVR controller at90can128, which has been strongly promoted by ATMEL in recent years, was selected.

AT90CAN128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC structure. By executing a single clock cycle of efficient instructions, AT90CAN128 can reach 1MIPS per MHz, which allows system designers to optimize power consumption and processing speed. The AVR core has a rich instruction set and 32 general-purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single clock cycle by executing a single instruction. As a result, the speed of this structure is 10 times faster than that of conventional RISC microcontrollers and the code efficiency is higher. In addition to the AD module and SPI module of the general AVR processor, it also integrates a CAN controller, which provides convenience for building a system based on CAN communication. The control structure is shown in Figure 2.

Figure 2 CAN control structure of at90can128.

The complex CAN communication protocol is not described in detail here. The following is an introduction to the use of the at90can128 CAN controller.

The CAN controller of the AT90CAN128 provides all the hardware that is conducive to message management. Each message to be sent or received is encapsulated by something called a message object. When initializing the module, the program will specify which messages to send and which messages to receive. Only those messages with agreed identifiers can be exchanged correctly. In addition, for the received remote frame, the controller will automatically reply accordingly.

Therefore, in this way, compared with the most primitive CAN control method, the CPU burden is greatly reduced. Users can meet their own requirements by configuring the relevant registers according to their own requirements.

Before sending a message, several fields must be initialized:

Among them, IDT is the identifier field, IDE is the identifier extension enable selection, RTRTAG is the remote transmission request, DLC is the data length code, RBnTAG is the reserved field (n = 0, 1), and MSG is the CAN data pointing to the corresponding MOB. When the send instruction of the MOB is executed, the MOB will be ready to send a data or a remote frame. Then, the CAN channel will scan each MOB, find the MOB with the highest priority, and send it out. When the transmission is successful, the TXOK bit in the MOB status register CANSTMOB will be set. And most importantly, for each new data transmission, the relevant registers must be reinitialized, otherwise it will not work properly.

The initialization steps before receiving a message are basically the same, except that the IDMSK and IDEMSK identifier mask settings are added.

The following is the key code and annotations based on the AVR at90can128CAN bus interface initialization and the sending and receiving function modules (see Figure 3).

Figure 3 CAN communication between the elevator system mainboard and the debugger.

CAN initialization:

CANGCON |= 0x01;

for( i = 0; i < 15; i + + )

{

CANPAGE = i<<4; // Initialize all 15 MOBs

CANCDMOB = 0;

CANSTMOB = 0;

CAN IDT1 = 0;

CAN IDT2 = 0;

…

for( j = 0; j < 8; j + + )

CANMSG = 0;

CANBT1= 0X1E; //Set CAN transmission baud rate, 16 divisions

CANBT2 = 0X40;

CANBT3 = 0X49;

CANPAGE = (0<<4); //Select MOB0 as the receiving MOB and set the identification code

CAN IDT1 = 0X00;

CAN IDM1 = 0X00;

…

CANPAGE = (1<<4); //Select MOB1 as the sending MOB, and set the identification code

CAN IDT1 = 0X00;

…

}

Send module code:

CANPAGE = (1<<4); //Select MOB1

If( ( CANGSTA& 0X10) == 0) //Query the TXBSY bit of the CAN status register. If it is 0, you can send

for( i = 0; i < 8; i + + )

{

CANMSG = my _dada[ i] ; // Load the data to be sent into the data register, a total of 8 bytes

CANCDMOB |= 0X48; //Send

}

The receiving module code is similar. The design idea is to load the data into the specified MOB after judging the send permission flag. Each MOB can send 8 bytes of data in one send cycle. The other end of the CAN bus is the CAN bus peripheral of NXP's LPC2294. Its structure and principle are similar. Of course, there will be a little difference in the register setting, but as long as the two CPUs agree on the identifier number of the data frame and the transmission rate is the same, data exchange can be carried out. Due to limited space, the CAN interface setting of LPC2294 will not be introduced here.

Finally, a hardware principle reference diagram of the CAN bus application CPU outside is given, as shown in Figure 4.

5 CAN bus transceiver TJA1050 hardware connection diagram

The CAN transceiver in the figure is NXP's TJA1050. TXD and RXD are connected to the CAN interface of the CPU respectively. CANL and CANH are buses connected to another CPU. The resistance between CANL and CANH is about 120 ohms. Switch S can be used as a hardware enable switch for the CAN bus. In addition, if the anti-interference requirements are high, photoelectric isolation can be used for TXD and RXD.

Figure 4. Hardware schematic diagram of CPU peripheral transceiver.

6 Conclusion

The elevator system debugger designed based on the CAN bus module of at90can128 has been tested for a long time and is in good condition with normal communication. Among the many field buses, the CAN bus has been recognized and preferred by more and more engineers due to its excellent characteristics. With the integration of more and more high-end CPUs on CAN controllers and the reduction of comprehensive costs, the use of CAN bus will surely become more and more common, and the 8-bit AVR with integrated CAN controller will also be favored by more and more people.