Altera offers C language hardware acceleration tool for Nois II processor

Altera Corporation today announced the availability of a new productivity tool for Nios II system developers, the Nios® II C-to-Hardware Acceleration (C2H) Compiler, which can effectively improve the performance of embedded software. As more and more embedded designs use FPGAs, the Nios II C2H Compiler is designed to help embedded system developers improve efficiency and achieve successful designs. As part of the Nios II C2H Compiler, Altera also allows third-party tool vendors to use its system-level infrastructure, including the Quartus® II SOPC Builder tool, to facilitate the development of a variety of electronic system-level (ESL) design tools. The

Nios II C2H Compiler leverages the Altera system-level infrastructure to effectively improve the performance of a variety of real-world applications. This new tool can automatically convert performance-intensive C language routines into hardware accelerators that are integrated into FPGA-based Nios II subsystems, reducing development time from weeks to minutes. The

Nios II C2H Compiler supports standard ANSI C code, which can accelerate the implementation of a variety of applications and improve their efficiency, including access to local and external memory and peripherals. It uses the high-bandwidth Avalon® interconnect architecture generated by the Quartus II SOPC Builder tool to successfully handle external memory operations, such as pointer scatter and array access. The Nios II C2H compiler analyzes the type of memory interface that the program is accelerating and generates hardware accelerator logic and appropriate Avalon master and slave interfaces to match the memory latency. This offloads the data computation and memory access functions of the Nios II processor, allowing the processor to better handle other tasks. Because the Avalon interconnect architecture does not limit the number of masters and slaves, the Nios II C2H compiler can generate multiple memory autonomous hardware accelerators based on the requirements of the converted target code. The Nios II C2H compiler

helps Nios II users achieve the goal of improving system performance with minimal resource usage. In fact, compared with unaccelerated software, the Nios II C2H compiler improves performance by 10 to 45 times, while occupying only 0.7 to 2.0 times more additional logic resources than the processor itself, and is suitable for a variety of software applications, including autocorrelation, bit allocation, convolutional coding, color space conversion, and fast Fourier transform (FFT).

The Nios II C2H compiler is a plug-in for the Eclipse-based Nios II Integrated Development Environment (IDE), and its interface is very familiar to Nios II software developers. All hardware acceleration generation tasks implemented by the Nios II C2H compiler can be called and run from within the Nios II IDE, ensuring that users can use the same tool to complete the entire acceleration process. After programming an application, users can use the Nios II C2H compiler to right-click on the time-critical function to accelerate and automatically link the hardware accelerator to the software process.

To enhance future work with partners and establish multiple ESL tools and methods that can be used together, Altera has opened the SOPC Builder system-level development tool and the Nios II IDE application programming interface (API). As a result, partners can take advantage of Altera's new Nios II C2H compiler system infrastructure to more rapidly develop tools, such as memory latency awareness and master-slave interface determination.

The Nios II C2H compiler is currently available to customers in beta and will be officially delivered in May 2006. The tool is delivered as a plug-in integrated with the Nios II IDE.