Summary table of register functions of 51 microcontroller

21 special function registers (26 for the 52 series) are discontinuously distributed in the 128-byte SFR storage space. The address space is 80H-FFH. This SFR space contains 128 bits of address space. It is also 80H-FFH, but there are only 83 valid bit addresses, which can perform bit addressing operations on certain bits of the 11 special function registers (here is a trick: any address whose address is divisible by 8 can be bit addressed).

There is a CPU inside the 51 microcontroller for calculation and control. There are four parallel I/O ports, namely P0, P1, P2, and P3. There is ROM to store programs and RAM to store intermediate results. In addition There are also timers/counters, serial I/O ports, interrupt systems, and an internal clock circuit. There are some independent storage units in the microcontroller used to control these devices, called special function registers (SFR). There are 21 such special function registers in the 51 microcontroller and they are all addressable. The list with * is the special function register added to the 52 series):

The respective descriptions are as follows:

1. ACC---is the accumulator, usually represented by A

What is this thing? You can’t understand it from the name. It is a register, not a thing that does addition. Why is it given such a name? Maybe it’s because one of the numbers must be in the ACC when the arithmetic unit is doing the operation. Probably because of it. Its name is special, and its identity is also special. We will learn instructions later in the middle part, and we can find that all computing instructions are inseparable from it. It has the all-zero flag Z. If A=0, then Z=1; if A≠0, then z=0. This flag is often used as a judgment condition for program branch transfer.

2. B--a register

When doing multiplication or division, put the multiplier or divisor. When not doing multiplication or division, use it however you want.

3. PSW-----Program status word.

This is a very important thing. It contains many states of the CPU when it is working. With this, we can understand the current state of the CPU and handle it accordingly. Please see the table below for its functions:

Below we introduce each of your uses one by one

CY: Carry flag.

The arithmetic unit in 8051 is an 8-bit arithmetic unit. We know that an 8-bit arithmetic unit can only represent 0-255. If addition is performed, the sum of the two numbers may exceed 255, so the highest bit will be lost. What should I do if an operation error occurs? The highest bit goes here. That'll be fine. With carry and borrow, CY=1; without carry and borrow, CY=0

Example: 78H+97H(01111000+10010111)

AC: Auxiliary carry and borrow (carry and borrow between high nibble and low nibble).

Example: 57H+3AH(01010111+00111010)

F0: User flag bit

It is up to the user (programmer) to decide when to use it and when not to use it.

RS1, RS0: Working register group selection bits

By modifying the status of the RS1 and RS0 bits in PSW, you can select any working register area. This feature increases the speed of MCS-51 on-site protection and on-site recovery. It is very beneficial to improve the efficiency of the CPU and the speed of responding to interrupts. If in an actual application system, four sets of working registers are not needed, then the excess units in this area can be used as general data buffers.

0V: overflow flag

The operation result is understood as two's complement operation. If there is overflow, OV=1; if there is no overflow, OV=0. What is overflow will be discussed in a later chapter.

P: parity bit

It is used to indicate the parity of the number of binary digits "1" in the ALU operation result. If it is an odd number, then P=1, otherwise it is 0. If the operation result has an odd number of 1's, P=1; if the operation result has an even number of 1's, P=0.

Example: The result of a certain operation is 78H (01111000). Obviously the number of 1's is an even number, so P=0.

4. DPTR (DPH, DPL)--------data pointer

It can be used to access any unit in the external data memory. If not used, it can also be used as a general register. It is up to us to decide how to use it. Divided into two registers: DPL (lower 8 bits) and DPH (high 8 bits). It is used to store 16-bit address values ​​in order to perform data operations within the 64K byte range of off-chip data RAM or program memory using indirect addressing or indexed addressing.

5. P0, P1, P2, P3--------Input and output port (I/O) registers

We already know this, it is the register of four parallel input/output ports (I/O). The content inside it corresponds to the output of the pin.

6. IE-----interrupt enable register

Bit addressable, address: A8H

● EA (IE.7): When EA=0, all interrupts are disabled (that is, no interrupts are generated); when EA=1, the generation of each interrupt is determined by individual enable bits

● - (IE.6): Reserved

● ET2 (IE.5): Timing 2 overflow interrupt enabled (for 8052)

● ES (IE.4): Serial port interrupt is enabled (ES=1 allows, ES=0 disables)

● ET1(IE.3): Timing 1 interrupt enabled

● EX1(IE.2): External interrupt INT1 interrupt enabled

● ET0(IE.1): Timer 0 interrupt enabled

● EX0(IE.0): Interrupt enable of external interrupt INT0

7. IP-----Interrupt priority control register

Bit addressable, address bit B8H

● - (IP.7): Reserved

● - (IP.6): Reserved

● PT2 (IP.5): Timing 2 interrupt priority (for 8052)

● PS (IP.4): Serial port interrupt priority

● PT1(IP.3): Timing 1 interrupt priority

● PX1(IP.2): External interrupt INT1 interrupt priority

● PT0(IP.1): Timer 0 interrupt priority

● PX0(IP.0): The interrupt of external interrupt INT0 has priority

8. TMOD-----Timer control register

Not bitwise addressing, address 89H

● GATE: Timing operation switch control bit. When GATE=1, the INT0 or INT1 pin is high level, and when the TR0 or TR1 control bit in TCON is 1, the timer/counter 0 or 1 starts to work. If GATE=0, as long as the TR0 or TR1 control bit is set to 1, the timer/counter 0 or 1 will start working.

● C/T: Selection bit for timer or counter function. C/T=1 is a counter, and the counting pulse is input through the external pin T0 or T1. When C/T=0, it is a timer, and the internal system clock provides timing pulses.

● M1, M0: T0, T1 working mode selection bits

9. TCON-----Timer control register

Bit addressable, address bit 88H

● TF1: Timer T1 overflow flag, which can be queried and cleared by the program. TF1 is also an interrupt request source and is cleared by hardware when the CPU responds to the T1 interrupt.

● TF0: Timer T0 overflow flag, which can be queried and cleared by the program. TF0 is also an interrupt request source and is cleared by hardware when the CPU responds to the T0 interrupt.

● TR1: T1 enables counting control bit. When it is 1, T1 counting is enabled.

● TR0: T0 enables counting control bit. When it is 1, T0 counting is enabled.

● IE1: External interrupt 1 request source (INT1, P3.3) flag. IE1=1, external interrupt 1 is requesting an interrupt from the CPU. When the CPU responds to the interrupt, the hardware clears IE1 to "0" (edge ​​trigger mode).

● IT1: External interrupt source 1 trigger mode control bit. IT1=0, the external interrupt 1 program control is level triggered. When INT1 (P3.3) inputs low level, IE1 is set.

● IE0: External interrupt 0 request source (INT0, P3.2) flag. IE0=1, external interrupt 1 is requesting an interrupt from the CPU. When the CPU responds to the interrupt, the hardware clears "0" IE0 (edge ​​trigger mode).

● IT0: External interrupt source 0 trigger mode control bit. IT0=0, the external interrupt 1 program control is level triggered. When INT0 (P3.2) inputs low level, IE0 is set.

10. SCON----serial communication control register

It is an addressable special register used for communication control of serial data. The unit address is 98H. Its structural format is as follows:

(1) SM0, SM1: Serial port working mode control bits.

SM0, SM1 working mode

00 Mode 0 - The baud rate is determined by the oscillator frequency: oscillator frequency/12

01 Mode 1 - The baud rate is determined by the overflow rate of timer T1 or T2 and SMOD: 2SMOD × (T1 overflow rate)/32

10 Mode 2 - The baud rate is determined by the oscillator frequency and SMOD: 2SMOD × oscillator frequency/64

11 Mode 3 - The baud rate is determined by the overflow rate of timer T1 or T2 and SMOD: 2SMOD × (T1 overflow rate)/32

(2) SM2: Multi-machine communication control bit. Multi-machine communication works in mode 2 and mode 3, and the SM2 bit is mainly used in mode 2 and mode 3. Receiving status, when the serial port works in mode 2 or 3, and SM2=1, only when the 9th bit of data received (RB8) is 1, the first 8 bits of data received are sent to SBUF and set Bit RI issues an interrupt request, otherwise the received data will be discarded. When SM2=0, no matter whether the bit data is 0 or 1, the data is sent to SBUF and an interrupt request is issued.

When working in mode 0, SM2 must be 0.

(3)REN: Allow receiving bit. REN is used to control the permission and prohibition of data reception. When REN=1, reception is allowed, and when REN=0, reception is prohibited.

(4)TB8: Send and receive data bit 8. In Mode 2 and Mode 3, TB8 is to be sent - the 9th data bit. This bit also needs to be transmitted in multi-machine communication, and it represents the transmitted address or data. When TB8=0, it is data, and when TB8=1, it is address.

(5)RB8: Receive data bit 8.

In Mode 2 and Mode 3, RB8 stores the 9th bit of data received to identify the characteristics of the received data.

(6)TI: Send interrupt flag bit.

Addressable flag bit. In mode 0, after the 8th bit of data is sent, it is set by hardware. In other modes, it is set by hardware before sending or stop bit. Therefore, TI=1 indicates the end of frame sending, and TI can be cleared to "0" by software.

(7)RI: receive interrupt flag bit.

Addressable flag bit. After receiving the 8th bit of data, this bit is set by hardware. In other working modes, this bit is set by hardware. RI=1 indicates that the frame reception is completed.

11. PCON-----power management register