Introduction to address space and MMU analysis of S3C2440 storage controller

1. S3C2440 storage controller

If you have written ARM bare metal programs for S3C2440, you should know that the starting address of SDRAM is usually 0X30000000, but have you ever thought about why? I will give you a brief introduction below.

Checking the S3C2440 manual shows that the S3C2440 can address an address range of 1G, but the S3C2440 has only 27 address lines. In theory, it can only address an address range of 2 to the power of 27, which is equal to 128M. So S3C2440 solved this problem through something called BANK. S3C2440 leads to 8 BANK lines (corresponding to nGCS0~nGCS7). Through these 8 lines, different memories are turned on and off. In this way, S3C2440 can connect up to eight 128M memories, as long as only one BANK is turned on at a certain time. It is possible to realize a 1G addressing space. Each BANK has an address. The access to the BANK address is actually to strobe the BANK. So the ARM core only needs to send out one address, and then the S3C2440 storage controller only needs to interpret the address into two Part: One part is the BANK address and the other part is connected to the address inside the BANK memory and can be accessed.

As a 32-bit CPU, the address range that can be used can theoretically reach 2 to the 32nd power, which is equal to 4G. In addition to the above-mentioned 1G address space, there is also a part of the address of the CPU's internal register, and the remaining address space is not used.

Let’s take a look at the address space distribution diagram of S3C2440 memory.

The left side is the address space diagram when the CPU starts from NOR FLASH, and the right side is the address space diagram when the CPU starts from NAND FLASH. It can be seen from the picture that SDRAM is connected to BANK6 with the address 0X30000000, which explains the original problem. The question comes again why the address space is different when the CPU boots from NAND and NOR? This is because NOR is a linear structure, similar to ordinary memory, and it is connected to BANK0. NAND is another structure. S3C2440 has a dedicated NAND controller and address line to connect it. It cannot be connected to BANK0. When the CPU starts, it must start executing the program from address 0, but when it starts from NAND, there is no memory at address 0, so what should the CPU do? So something called the "stepping stone" appeared, which is a 4K memory inside the S3C2440. When booting from NAND, the 0 address line will be connected to the stepping stone, and the CPU will pass the internal The hardware copies the 4K data starting from NAND FLASH to the starting stone. The program in the starting stone is generally designed to initialize the SDRAM, then copy part of the program in the NAND to the SDARM, and then jump to the SDRAM to start executing the program. Therefore, when transplanting U-BOOT to support booting from NAND, the first 4K program of NAND needs to be processed.

Next, let’s take a look at the access addresses of peripherals generally connected to the S3C440 memory controller and the access addresses of some registers.

2. S3C2440MMU

1.The role of MMU

All we discussed in the first part are physical addresses. Be careful not to confuse them with the virtual addresses we will discuss in this part.

Memory Management Unit (Memory ManagerUnit) is referred to as MMU. It is responsible for converting virtual addresses into physical addresses and then passing them to the storage manager introduced in the previous section for addressing.

Modern multi-user multi-process operating systems use MMU to allow each user process to have its own independent address space: the address mapping function allows each process to have the same address space, and the check of memory access permissions can protect each process. The memory used by one process will not be destroyed by other processes.

Let me give you a lame example. Classmate A (Process A) went to a librarian to borrow a book called "Memory" and said that he would use it at 7 o'clock. The librarian gave Student A a sign that said which floor and room contained the book. However, this sign could only be picked up at 7 o'clock and could only be borrowed for three hours (authority). Student B also had to The book can only be borrowed at 12 o'clock. The library also gives Student B a sign. However, when the sign is different, the book can only be picked up at 12 o'clock and can only be borrowed for three hours. As a result, both students A and B borrowed the book. They all felt that they owned the book and would not be disturbed by other students while they owned the book. In fact, the classmates here represent the process, the librarian represents the kernel, the brand represents the virtual address, and the book represents the actual memory, and the work completed by MMU is to get the classmate's sign to help the classmate find the book.

The virtual address must eventually be converted into a physical address before actual data can be read and written. By dividing the virtual address space and the physical address space into small spaces of the same size, and then establishing mapping spaces for the two types of small spaces, it is possible to Block virtual addresses are mapped to the same physical address space, or some virtual address spaces are mapped to specific physical address spaces. After starting the MMU, the CPU sends out a virtual address, and then the MMU converts the virtual address into a physical address before accessing it.

2. The conversion process from virtual address space to physical space

In ARM CPU, page table is used for conversion. The Linux kernel generally uses a two-level page table. What is a page table? It is like the table of contents in our books, with a main directory and a subdirectory. When we want to find a knowledge point, we first find the main directory, then find the secondary directory and then find the corresponding knowledge point. Each process will create a directory in the memory, and the storage address of the directory is saved. When we need to access a directory, the directory will be placed in a special register of the CPU, and then the MMU will read the value in this register and help us find the physical address we want to access.

How is the page table created?

In fact, it stores the memory address of the first-level directory in an address in the memory, and then stores the actual physical address in the memory of the first-level directory.