Study Notes - Detailed Explanation of 51 MCU IO Ports

Preface

The control of the MCU is actually the control of the I/O port. No matter what kind of control the MCU performs on the outside world, or what kind of control it accepts from the outside, it is all done through the I/O port. The structure of each IO port of the 51 MCU is different, and each has its own characteristics. In daily applications, especially when designing peripheral hardware, if you don’t understand its internal structure, there may be problems in the design (especially when using the P0 port), so it is very necessary to understand the structure of each port. Another point is that the pins of the 51 MCU do not support remapping like the STM32, so this should also be paid attention to when laying out the hardware. The following is some information found on the Internet, organized as follows:

Internal structure of 51 MCU I/O port

1.1 Structure and working principle of P0 port

Structure diagram of one of the 8 bits of port P0

As can be seen from the figure above, the P0 port is composed of a latch, an input buffer, a switch, a NAND gate, an AND gate and a field effect transistor drive circuit. On the right side of the figure, there is an icon labeled P0.X pin, which means that the P0.X pin can be any one of P0.0 to P0.7, that is, there are 8 circuits in the P0 port that are the same as the above figure.

Next, we will introduce each unit that makes up the P0 port:

- Input buffer: There are two three-state buffers in the P0 port. The three-state gate has three states, that is, the output can be high level, low level, and there is also a high impedance state (or forbidden state). To read the data at the output end Q of the D latch, the three-state control end of the buffer of the read latch (labeled as "read latch" in the figure above) must be enabled. The next one is the buffer of the read pin. To read the data on the P0.X pin, the control end of the three-state buffer labeled "read pin" must also be enabled, and the data on the pin will be transmitted to the internal data bus of our microcontroller.

- D latch: To form a latch, a timing circuit is usually used. A trigger can save a binary number of one bit (i.e., it has a holding function). In the 32 I/O lines of the 51 single-chip microcomputer, a D trigger is used to form a latch. In the D latch in the figure above, the D terminal is the data input terminal, the CP is the control terminal (i.e., the timing control signal input terminal), the Q is the output terminal, and the Q is the reverse output terminal. For the D trigger, when there is an input signal at the D input terminal, if there is no signal at the control terminal CP at this time (i.e., the timing pulse has not arrived), the data at the input terminal D cannot be transmitted to the output terminal Q and the reverse output terminal Q. If the timing pulse of the timing control terminal CP arrives, the data input at the D terminal will be transmitted to the Q and Q terminals. After the data is transmitted, when the timing signal of the CP timing control terminal disappears, the output terminal will still maintain the data of the last input terminal D (i.e., the last data is latched). If the next timing control pulse signal comes, the data at the D terminal will be transmitted to the Q terminal again, thereby changing the state of the Q terminal.

- Multiplexer: In the 51 MCU, when the internal memory is sufficient (that is, when there is no need for external memory expansion, the memory here includes data memory and program memory), the P0 port can be used as a general input and output port (i.e. I/O). For the 8031 ​​MCU (without internal ROM) or the program written exceeds the internal memory capacity of the MCU, when external memory expansion is required, the P0 port is used as the 'address/data' bus. Then this multiplexer is used to select whether to use it as a normal I/O port or as a 'data/address' bus. In the above figure, when the multiplexer is connected to the bottom, the P0 port is used as a normal I/O port, and when the multiplexer is connected to the top, the P0 port is used as an 'address/data' bus.

- Output drive part: As we can see from the above figure, the output of P0 port is a push-pull structure composed of two MOS tubes, that is, these two MOS tubes can only be turned on one at a time. When V1 is turned on, V2 is turned off, and when V2 is turned on, V1 is turned off.

- AND gate, NAND gate: Gate circuit is an integrated circuit that acts as a switch. According to different opening conditions, it is divided into AND gate, NOT gate, NAND gate, etc. The knowledge points here are relatively simple, so I will not explain them in detail here.

1.2 Working principle when P0 is used as an I/O port

1.2.1 Working principle of P0 when used as a normal I/O port

When the P0 port is used as an I/O port, the control signal of the multiplexer is 0 (low level). The control signal of the multiplexer is connected to one of the input terminals of the AND gate at the same time. We know that the logical characteristic of the AND gate is "all 1s output 1, all 0s output 0". If the control signal is 0, the output of the AND gate is also a 0 (low level). When the output of the AND gate is 0, the V1 tube is cut off. When the control signal of the multiplexer is 0 (low level), the multiplexer is connected to the Q non-terminal of the latch (that is, the P0 port is used as an I/O port line).

- When the P0 port is used as an I/O port, the working process of the data bus outputting to the pin (i.e., output state Output) is:

When the write latch signal CP is valid, the signal of the data bus → the input terminal D of the latch → the reverse output Q non-terminal of the latch → the multiplexer → the gate of the V2 tube → the drain of V2 to the output terminal P0.X. We know that when the control signal of the multiplexer is low level 0, the AND gate output is low level, and the V1 tube is cut off, so when used as an output port, P0 is an open drain output, similar to an OC gate. When driving a current load, an external pull-up resistor is required.

Port P0 is used as an I/O port line, and its working process of inputting from the pin to the internal data bus (i.e. input state Input) is as follows:

There are two situations when data is input (reading P0 port)

1. Read pin

To read the data on the chip pins, when reading the pin number, the pin read buffer is turned on (that is, the control end of the three-state buffer must be valid) and input through the internal data bus.

2. Read latch

The state of the latch output Q is read by opening the read latch tri-state buffer.

In the input state, the signals read from the latch and the pin are generally consistent, but there are exceptions. For example, when a low level is output from the internal bus, the latch Q = 0, Q non = 1, the field effect transistor T2 is turned on, and the port line is in a low level state. At this time, no matter whether the external signal on the port line is low or high, the signal read from the pin to the microcontroller is low, so the signal on the port pin cannot be read correctly. For another example, when a high level is output from the internal bus, the latch Q = 1, Q non = 0, and the field effect transistor T2 is turned off. If the external pin signal is low, the signal read from the pin is different from the signal read from the latch. For this reason, the 8031 ​​microcontroller has the following agreement on the input operation of ports P0-P3: For this reason, the 8051 microcontroller has the following agreement on the input operation of ports P0-P3: For instructions belonging to the read-modify-write mode, the signal is read from the latch, and other instructions read the signal from the port pin line.

The characteristic of the read-modify-write instruction is that the signal is input (read) from the port, calculated (modified) in the microcontroller, and then output (written) to the port. The reason for this arrangement is that the read-modify-write instruction needs to obtain the original output state of the port, modify it and then output it. Reading the latch instead of the pin can avoid the original port state being read incorrectly due to external circuit reasons.

1.2.2 Working principle when P0 is used as address/data multiplexing port

At this time, the 'control' signal of the multiplexer is '1', the 'AND gate' is unlocked, and the output signal level of the 'AND gate' is determined by the "address/data" line signal; the multiplexer is connected to the output end of the inverter, and the address signal is output via the "address/data" line → inverter → V2 field effect transistor gate → V2 drain.

When P0 is used as the address/data bus, the CPU automatically writes 0FFH to the P0 port latch before reading the instruction code or inputting data, destroying the original state of the P0 port. Therefore, it can no longer be used as a general I/O port. In the future, when designing the system, be sure to pay attention to the fact that the program cannot contain instructions that use the P0 port as an operand (including source operands and destination operands).

When the control signal is 1 and the address signal is "0", the AND gate outputs a low level, and the V1 tube is cut off; the inverter outputs a high level, the V2 tube is turned on, and the address signal of the output pin is a low level. (The blue font is the level)

On the contrary, when the control signal is "1" and the address signal is "1", the output of the "AND gate" is high level, and the V1 tube is turned on; the inverter outputs a low level, the V2 tube is turned off, and the address signal of the output pin is high level. Please see the figure below (the blue font is the level)

It can be seen that when outputting "address/data" information, V1 and V2 tubes are turned on alternately, and have a strong load capacity. They can be directly connected to the external memory without adding a bus driver.

Port P0 is also used as a data bus. When accessing external program memory, after port P0 outputs the lower 8 bits of address information, it will become a data bus to read the instruction code (input).