5. ATD0 status register 5 --- ATD0START0, ATD0START0
ATD0START0 reflects the current conversion channel, whether the A/D conversion is completed, whether there is an external trigger, etc.;
ATD0START1 reflects whether the corresponding conversion in the conversion sequence is completed. Register ATD0START0,
SCF ---Conversion sequence completed flag
In single conversion mode, it is set when the conversion is completed (SCAN = 0).
In continuous conversion mode, it is set when the first conversion is completed (SCAN = 1). When AFFC = 0, writing 1 clears it.
ETORF --- External trigger override flag
If a high/low level occurs during the conversion process, FIFOR is set.
Set when the result register has been written before being read (CCF is not cleared)
CC[2:0] Conversion Counter --- 3-bit counter pointing to the next channel to be converted
CCF7 -CCF0 --- Independent channel conversion completion flag. Set when the corresponding channel conversion is completed. Clear when the corresponding A/D result register is read out. Note the situation when the AFFC bit is different.
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