MC9S12G128 modular layered software architecture 5 - IO optimization

1 overview

1.1 Purpose

This document is used to explain the software optimization of the GPIO module of the Qidian development board.

It is not limited to the realization of hardware functions, but focuses on the realization of high-quality and beautiful software.

2. Optimize content

2.1 Software Features

①Add the relevant configuration of PORTA, PORTB, PORTC, PORTD and PORTAD pins;

②The driver layer and module layer are adjusted according to the newly added PORT;

2.2 Programming Robustness

①Add const modifier before constant;

②Add static before the variables and functions that are only used in this file;

3 Software Implementation

3.1 CodingRule

The details can be seen in the .MC9S12G128_IO_optimizeSourcescode_rules.txt of the source code.

3.2 Driver Layer Optimization

3.2.1 drio_cfg.c

3.2.1.1 drio_dir_reg[] direction register optimization

The changes are as follows:

①Add const modifier;

②Add DRIO_HAS_PORTA2D macro configuration;

③Add two registers, DDR1AD and DDR0AD, for PORTAD pin settings;

Modify reason:

①Reasons for adding const:

According to the coding rule, for constants, const modifier needs to be added;

②Reason for adding DRIO_HAS_PORTA2D:

For MC9S12G128 with different pins, the 100-pin has PORTA to PORTD, but the 64-pin does not, so a macro can be added here to configure it during pre-compilation;

③Add two registers DDR1AD and DDR0AD:

PORTAD has 16 pins, the direction register corresponding to DRIO_PIN0 to DRIO_PIN7 is DDR1AD; the direction register corresponding to DRIO_PIN8 to DRIO_PIN15 is DDR0AD;

3.2.1.2 drio_data_reg[] data register optimization

The changes are as follows:

① Add const modifier;

②Add DRIO_HAS_PORTA2D macro configuration;

③Add two registers, PT1AD and PT0AD, for PORTAD pin settings;

Add PT1AD and PT0AD. Reasons for modification:

PORTAD has 16 pins, the data register corresponding to DRIO_PIN0 to DRIO_PIN7 is PT1AD; the data register corresponding to DRIO_PIN8 to DRIO_PIN15 is PT0AD;

3.2.2 drio_cfg.h

3.2.2.1 Macro definition DRIO_HAS_PORTA2D

The changes are as follows:

As can be seen from the figure below, the pins in MC9S12G128 are not only PORTE, PORTT, PORTS, PORTM, PORTP, PORTJ, but also PORTAD. If the pin number is 100, there are also PORTA, PORTB, PORTC, and PORTD. However, due to the limitation of the number of pins, not all MC9S12G128 have PORTA to PORTD, so macros can be used to configure whether there are PORTA to PORTD.

The original drio_cfg.h only has PORTT, PORTS, PORTM, PORTP, PORTJ, and now PORTAD and PORTA, PORTB, PORTC, PORTD are added.

PORTAD is a special PORT because it has 16 pins. Its registers are as follows:

In order to facilitate the driver layer to call the drio_dir_reg[] level register array for indexing without having to process PORTAD separately, PORTAD is divided into DRIO_PORTAD and DRIO_PORTAD_DUPLICATE. When the upper module layer calls, it only needs to select the DRIO_PORTAD port. When the pin is greater than DRIO_PIN7, the port is increased by one and becomes DRIO_PORTAD_DUPLICATE to index drio_dir_reg[] and drio_data_reg[]. The changes of these two register arrays can be seen in drio_cfg.c.

3.2.2.2 Enumerate DRIO_PIN

The changes are as follows:

Since POATAD consists of 16 pins, when configuring GPIO at the module level, you don't have to worry about whether to use PT0AD or PT1AD when selecting pins, but only need to choose DRIO_PORTAD and DRIO_PIN0 or DRIO_PIN15. Because in the schematic diagram and the chip manual pin configuration diagram, there are only PAD0 to PAD15, as shown below:

As for how to set the corresponding direction register and data register, it has been set in drio_cfg.c and drio.c. For details, please refer to the drio_cfg.c and drio.c chapters.

3.2.2.3 Declaring extern

3.2.3 drio.c

Change log:

3.2.3.1 drio_set_pin_input

The changes are as follows:

In addition to the validity checks for the port range and pin range, port handling is added for DRIO_PIN8 to DRIO_PIN15 of PORTAD. The reasons are visible in drio_cfg.h and drio_cfg.c;

The validity check of the port range and pin range is to prevent the drio_dir_reg[] array from crossing the boundary. In fact, the upper module layer has already done the anti-crossing process, so it can be omitted here.

3.2.3.2 drio_set_pin_output optimization

3.2.3.3 drio_set_pin_value optimization

3.2.3.4 Add drio_read_pin

Prepare for the key acquisition of reading pin levels in the next section.

3.3 Middleware module layer optimization

3.3.1 mdio_cfg.c optimization

Add const modifier to constants.

as follows:

3.3.2 mdio_cfg.h

extern variable declaration

3.3.3 mdio.c

3.3.3.1 Optimization of io initialization function mdio_init

Pointer to a constant

4 Software testing and debugging

4.1 PORTAD Verification Code

After adding PORTAD, in order to verify that PORTAD can correctly set the direction register and data register, add the output settings of PORTAD in drio_cfg.c as follows:

4.2 MCU register

4.2.1 DDR Data Direction Register

PORTAD direction registers DDR1AD and DDR0AD. As can be seen from the figure, we need each bit of DDR1AD and DDR0AD to be 1, that is, output. During debugging, we can see that each bit of DDR1AD and DDR0AD is 1.

4.2.2 Data Register

According to the configuration in mdio_cfg.cz, PT1AD should be 0x55, PT0AD should be 0xff, and debug can show the following:

According to the schematic:

The test shows that the pin levels on the left side from AN0 to AN7 are 1 0 1 0 1 0 1 0, corresponding to PT1AD is 0x55, and the pins on the right side are all high levels.