ARM processor exception handling steps

Introduction: The processor allows multiple exceptions to occur simultaneously, and they will be processed according to a fixed priority. When an exception occurs, the ARM microprocessor will perform the following steps:

ARM processor status, instruction set

ARM microprocessors generally have two working states and can switch between the two states:

The first is the ARM state, in which the processor executes 32-bit word-aligned ARM instructions, corresponding to the ARM instruction set;

The second is the Thumb state, in which the processor executes 16-bit, half-word aligned Thumb instructions, corresponding to the Thumb instruction set.

During the execution of the program, the microprocessor can switch between the two working states at any time, and the change of the processor working state does not affect the processor's working mode and the contents of the corresponding registers. However, the ARM microprocessor should be in the ARM state when it starts executing the code.

The ARM processor has a total of 37 registers. These include: 31 general registers, including the program counter (PC). These registers are all 32-bit registers. And 6 32-bit status registers. I won't go into detail about the registers here. If you are interested, you can search the Internet for a lot of information on this.

Exception handling

When the normal program execution flow is temporarily stopped, it is called an exception, such as processing an external interrupt request. Before processing the exception, the current processor state (CPSR) must be retained so that when the exception is processed, the current program can continue to execute. The processor allows multiple exceptions to occur at the same time, and they will be processed according to a fixed priority. When an exception occurs, the ARM microprocessor will perform the following steps:

The basic steps to enter exception handling:

Store the address of the next instruction in the corresponding link register LR (Link Register) so that the program can restart execution from the correct position when handling an exception return. Copy the CPSR to the corresponding SPSR. According to the exception type, force the operating mode bit of the CPSR to be set. Force the PC to fetch the next instruction from the relevant exception vector address and jump to the corresponding exception handler. If the processor is in Thumb state when an exception occurs, the processor automatically switches to ARM state when the exception vector address is loaded into the PC. The response process of the ARM microprocessor to an exception can be described in pseudo code as follows:

R14_ = Return Link

SPSR_= CPSR

CPSR[4:0] = Exception Mode Number

CPSR[5] = 0; when running in ARM working state

If == Reset or FIQ then; when responding to a FIQ exception, new FIQ exceptions are prohibited

CPSR[6] = 1

PSR[7] = 1

PC = Exception Vector Address

After the exception is handled, the ARM microprocessor will perform the following steps to return from the exception:

Subtract the corresponding offset from the value of the link register LR and send it to the PC.

Copy the SPSR back into the CPSR.

If the interrupt disable bit is set when entering exception processing, it must be cleared here.