Interrupt processing based on IRQ in ARM

Startup interrupt vector table

;*******************************************************************************

; ExcepTIon vectors

;*******************************************************************************

LDR PC, Reset_Addr; address is 0x8000 0000

LDR PC， Undefined_Addr

LDR PC， SWI_Addr

LDR PC， Prefetch_Addr

LDR PC， Abort_Addr

NOP ; Reserved vector

LDR PC， IRQ_Addr

LDR PC， FIQ_Addr

; *******************************************************************************

; ExcepTIon handlers address table

;*******************************************************************************

Reset_Addr DCD __program_start ; the address is 0x8000 0020

Undefined_Addr DCD UndefinedHandler

SWI_Addr DCD SWIHandler

Prefetch_Addr DCD PrefetchAbortHandler

Abort_Addr DCD DataAbortHandler

DCD 0 ; Reserved vector

IRQ_Addr DCD IRQHandler

FIQ_Addr DCD FIQHandler

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; Peripherals IRQ handlers address table

;*******************************************************************************

PRCCUCMU_Addr DCD PRCCUCMUIRQHandler; the address is 0x8000 0040

For embedded systems, the code generated above is usually placed in the flash at address 0x8000 0000 (the sector is also remapped to 0x0000 0000). The addresses of __program_start, UndefinedHandler, etc. are placed in the instruction buffer pool. This allows global jumps. According to the ARM instruction length, the physical address of the address of __program_start is 0x8000 0020. According to the ARM pipeline, LDR PC, Reset_Addr generates assembly language instructions such as LDR PC, [PC, #24].

When an IRQ interrupt occurs, the program jumps to the IRQHandler.

IRQHandler

IRQHandler

SUB lr，lr，#4 ; Update the link register

SaveContext r0，r12 ; Save the workspace plus the current

; return address lr_ irq and spsr_irq.

LDR lr， =ReturnAddress; Read the return address.

LDR r0， =EIC_base_addr

LDR r1， =IVR_off_addr

ADD pc，r0，r1 ; Branch to the IRQ handler.

ReturnAddress

; Clear pending bit in EIC （using the proper IPRx）

LDR r0， =EIC_base_addr

LDR r2， ［r0， #CICR_off_addr］ ; Get the IRQ channel number

CMP r2，#31

subhi r2, r2, #32

MOV r3, #1

MOV r3，r3，LSL r2

STRHI r3，［r0， #IPR1_off_addr］ ; Clear the corresponding IPR bit.

STRLS r3，［r0， #IPR0_off_addr］ ; Clear the corresponding IPR bit.

RestoreContext r0，r12 ; Restore the context and return to the.。。

; 。。.program execuTIon.

Among them, EIC_base_addr is 0xFFFF FC00, and the address of IVR is 0xFFFF FC18. By executing the instructions in this register, you can enter the corresponding interrupt service program. This register can be set when installing the interrupt vector service program. For example, if the value of the IVR register is 0xE59FF468, it means LDR PC, [PC, #1128]. In fact, it jumps to the TImer2 interrupt service program defined in the instruction buffer.

Interrupt Vector Register and Source Interrupt Registers Settings

extern u32 PRCCUCMU_Addr;

u8 Counter=0;

u32 Offset = (u32) & PRCCUCMU_Addr; //PRCCUCMU_Addr address is 0x8000 0040

u32 Tmp=0;

/* IVR = high half of load PC instruction （LDR PC，） */

EIC-》IVR = 0xE59F0000; //0xE59F0000, according to the instruction format, indicates an unsigned

//The instruction is executed, which transfers the value to the destination register PC.

//F in the instruction means r15, i.e. PC

/* Read the offset of the interrupt vectors table address */

Offset = (Offset + 0x3E0) < < 16; // Why do we need to add 0x3E0 to the offset address?

//0x8000 0040 + 0x3E0 《《 16 = 0x0420 0000，

//After an interrupt occurs, the high 16 bits of SIR will be passed to the low

//16bit is used as the offset address, and the IVR address is 0xFFFF FC18

//0xFFFF FC18 + 0x420 + 0x8 (pipeline impact) =

//0x1 0000 0040, since ARM is 32 bits, it is

//0x40 (this address is also mapped to 0x8000 0040)

/* Initialize SIRn registers with the equivalent low half of load PC instruction */

for（Counter=64; Counter！=0; Counter--）

{

EIC-》SIRn［64-Counter］ = Offset|0xF0000000; //Why 0xF000 0000? It is because LDR PC, ［PC, #0ffset］,

//The source register and the destination register are both PC

Offset += 0x00000004 《《 16;

}

The above program snippet sets IVR and SIRn, etc. In this way, when an IRQ interrupt occurs, the PC first jumps to 0xFFFF FC18, that is, the instruction LDR PC, [PC, #offset] in the IVR register is executed, and the address of the interrupt service routine is taken from the instruction buffer pool to the PC, thereby jumping to the interrupt service routine.