STM8 interrupt sources

STM8 interrupt sources

The STM8 interrupt controller handles 2 types of interrupt sources:

• Non-maskable interrupts: RESET, TLI, and TRAP
  

• Maskable interrupt: External interrupt or embedded peripheral interrupt
  Non-maskable interrupt source
  Non-maskable interrupt does not consider the status of I1 and I0 of CC register (see Figure 17). Only when TRAP interrupt occurs, the
  contents of PC, X, Y, A and CC registers are pushed onto the stack. The corresponding vector is loaded into PC register and I1 and I0 bits are set to disable interrupt (3 levels of priority).


(Figure 17: Interrupt processing flow chart)

• TRAP (non-maskable software interrupt)
  responds to software interrupt when TRAP instruction is executed. Its response process is shown in the flowchart of Figure 17.
  TRAP interrupt cannot cause the processor to exit from Halt mode.
  

• RESET
  Reset interrupt is the highest priority of STM8 software and hardware interrupts, which means that all interrupts are disabled at the beginning of the reset procedure. They must be enabled by the RIM instruction (see Table 15).
  Reset interrupt can exit the processor from Halt mode.
  For more detailed reset interrupt management, see the reset chapter.
  

• The highest level hardware interrupt of TLI
  will generate a hardware interrupt when a specific I/O edge is detected on the corresponding TLI input.
  Note: The TRAP instruction is prohibited in the TLI interrupt service routine.
  Maskable interrupt sources
  For maskable interrupts, if the corresponding interrupt is enabled, and if the interrupt priority in the ITC_SPRx register is higher than the priority of the currently executing interrupt (according to the I1 and I0 bits of the CC register), it can be responded to. If any of the above 2 conditions is not met, the interrupt will be latched and kept in the waiting state.
  

• External interrupts
  can be used to wake up the MCU from Halt mode. The selection of external interrupt triggering mode can be achieved by software writing to the external interrupt control register (EXTI_CRx).
  When multiple external pin interrupts connected to the same interrupt vector are selected at the same time, they are in a 'logical or' relationship.
  When the external level-triggered interrupt is latched, if the given level is maintained until the end of the interrupt subroutine, the level signal will trigger the interrupt again, unless the interrupt is disabled in the interrupt subroutine.
  

• Peripheral interrupts
  Most peripheral interrupts will cause the MCU to wake up from Halt mode.
  A peripheral interrupt is generated when the interrupt flag bit of the corresponding peripheral status register is set and the enable bit of the corresponding peripheral control register is set. The
  standard sequence for clearing an STM8 peripheral interrupt is to read or write the relevant registers after accessing the status register.
  When a clearing process is executed, the corresponding pending interrupt (an interrupt that will be executed) will be lost.
  

(Table 15: Dedicated interrupt instruction set)