ARM learning interrupt architecture

This afternoon and evening, I have been studying the s3c2410 interrupt architecture. Although I have been exposed to it in the teacher's class and have taken the exam before, I have gained a lot from studying it carefully. Now I will record it as follows:

1. What is an interrupt? 
Answer: An interrupt is a mechanism used by the CPU to ensure concurrent programs. It enables the CPU to respond to abnormal situations when executing programs. 
In fact, when the CPU is running, how can it know that some unexpected things have happened to various peripherals, such as the serial port receiving data, the device being inserted into the USB interface, and the pressing of a certain button. There are two methods, one is the interrupt mentioned above, and the other is the polling method. (That is, continuous while loop query). To some extent, these two methods are actually the same. The former is to narrow the query time span to after each instruction is executed, that is, when an event occurs, the hardware will set a register; after each instruction is executed, the CPU checks this register through the hardware to "query" whether there is an event of interest.

2. What is the basic interrupt processing flow of s3c2440? 
Answer: As shown in the figure below. 

I understand it simply like this: s3c2440 has two types of interrupt sources. Sub-interrupt sources and ordinary interrupt sources. If an interrupt request occurs for sub-interrupt sources of similar types, they will be aggregated into a "large" ordinary interrupt source (I don't know if this description is appropriate). Of course, this is under the condition that the sub-interrupt source is not masked. It is still quite difficult for the interrupt request of this sub-interrupt source to succeed. It has to go through two hurdles. First, the sub-interrupt source mask register cannot mask it, and then the interrupt mask register cannot mask it either. Only then can it be "favored" by the CPU (of course, it still has to compete with a large number of other request sources that 
request ). Ordinary interrupt sources are equivalent to "concubines". As long as there is a request and the priority is high, they can be "favored" by the CPU. There is also a queen-level interrupt source, called a fast interrupt source. She is quite awesome. As long as she requests, the CPU will "visit her". (It's like a palace drama).

3. When an interrupt occurs, how do we program? 
Answer: When an exception occurs, the ARM CPU will automatically complete the following things (remember, it is automatic): 
(1) The lr register saves the address of the next instruction of the current instruction. Usually (PC+4 or PC+8) 
(2) The value of CPSR is copied to SPSR. 
(3) The working mode bit of CPSR is set to the working mode corresponding to the exception. 
(4) Switch to execute the corresponding instruction in the vector table corresponding to this exception (not just the interrupt handling function).

For us, we need to complete the following things at the address corresponding to the exception vector table: 
(1) Save the running environment. The running environment mentioned here refers to the running environment in the previous mode. Although this has entered the exception mode, since the exception mode and the normal mode share some registers, these registers in the exception mode here also save the data in the previous mode, so they must be saved to the stack. 
(2) Enter the ISP function. That is, the interrupt processing function written by yourself to handle the interrupt. 
(3) In the interrupt processing function, it is necessary to determine which interrupt source issued the request (if the interrupt source is very clear, there is no need to determine), formally process the interrupt request (receive data, send data, light up the light, etc.), and finally don’t forget to clear the interrupt source. 
(4) Return from the interrupt and restore the saved running environment.

4. What is the interrupt vector table? 
Answer: The interrupt vector table is the address of the interrupt vector entry that the CPU will find according to the interrupt vector table after an interrupt occurs, and continue to execute at this address. When I was in class before, I thought it was so mysterious. Wow, the interrupt vector table is implemented in hardware. Now I see that it is not very difficult (at least for ARM9). In short, the interrupt vector table is not a real table. It is just specified in advance. If this interrupt occurs, it will continue to execute at this address. It looks like a table is mapped, and it can be regarded as a logical table. After an interrupt occurs, the CPU will continue to execute at the specified address. Therefore, you must write your interrupt handling function at this address. If there is nothing at this address, then the program will die.