ARM remap and relocation excerpt

(I) Understanding of ARM processor Remap
0. What is Remap
    My understanding is: after the ROM boots the system with a few instructions from 0x0, mapping RAM to 0x0 is Remap.
1. The role of Remap
    When the ARM processor is powered on or reset, the processor fetches instructions from 0x0. Therefore, it must be ensured that there are instructions at 0x0 that can be executed when the system is powered on. Therefore, when powered on, the address 0x0 must be ROM or Flash (NOR).
    However, in order to speed up the startup speed and to facilitate the change of the exception vector table and speed up the interrupt response speed, the exception vector table is often mapped to a faster and wider (32bit/16bit) RAM. However, the starting address of the exception vector table is determined by the ARM architecture and must be located at 0x0, so the RAM must be mapped to 0x0.
2. Remap configuration
    The implementation of Remap is related to the implementation of the ARM processor.
    1) If the processor has a dedicated register to complete Remap. Then Remap is completed by setting the corresponding bit of the Remap register to 1. Such as Atmel AT91xx
    2) If the processor does not have a dedicated register, but the memory bank control register can be used to configure the bank's start address, then remap can be completed by programming the RAM's start address to 0x0. Such as Samsung S3C4510
    3) If neither of the above two mechanisms exists, then remap is not necessary. Because the processor implementation determines that the SDRAM corresponding bank address cannot be changed. Such as Samsung S3C2410.
3. Work to be done before and after remap configuration
    Before and after remap, the difference is that the RAM location has changed. In order to achieve the purpose of remap, which is to speed up the startup speed and exception handling speed, the exception stack must be initialized and the exception vector table must be established.
4. What if it cannot be remapped like 2410?
    Isn't 2410 unable to remap? In order to speed up the startup speed, you can do this
    1) Use its NAND boot mode. Why NAND boot is faster? That's because there is a small stone in 2410 - "SteppingStone", a 4KB SRAM, which is mapped at 0x0. The boot program will be automatically copied to this stone. The entry of the natural exception vector is placed here, which can also achieve a faster startup and exception response speed than NOR boot.
    2) If you are devoted to NOR Boot, then you have to copy the entry of your exception vector to SDRAM to achieve the so-called High Vector

My understanding of relocation:

Regarding relocation, based on NOR BOOT, it is necessary to calculate the offset after the code is moved, and the global variable address needs to be added to this offset. Global variables are divided into initialized and uninitialized global variables, RO, RW, BSS

(II) How to use ads (axd) correctly 
1. ads is a compilation and debugging environment provided by ARM. It is very good and cannot be questioned! People who develop ARM cannot do without ads. For example, if you want to develop a driver, you must first compile and debug it in ads before adding it to the operating system. This is the development process. 2. Codewarria in ads is the compilation environment. In this environment, the address of program work or debugging should be set correctly. These two addresses are not necessarily the same address. Only one can be set at a time unless they are the same. The setting is done through the menu item edit->target setting. This address in the compilation environment is marked on the program by the linker (let's say this for now, because this part actually involves the link positioning problem in the compilation principle, which mainly involves the jump address in the program, which is related to the software). Both addresses must be coordinated with the hardware address for the program to work properly. Because mcu (arm) is hardware addressing, for example, after the normal initialization of 4510, the flash is located at address 0x0. At this time, if the mcu has an instruction to jump to address 0x0, then the mcu will definitely point the PC to address 0x0 of the flash, but the mcu is controlled by software. If remap is performed at this time, the flash is located at address 0x1000000, but the program written in the flash still controls the mcu to jump to address 0x0, then the PC points to address 0x0 of sdram, and what is written there is your business. 
3. The working address refers to the address where the compiled program (usually *.bin file) is written to the flash. If the working address of the software program starts from 0x0, the flash should also be located at address 0x0. The software and hardware addresses must be the same to work properly. Of course, if you do remap and copy the program to the new address 0x0, that is, in sdram, the program can also work normally. 
4. If you use axd for debugging, it is another case: the program must be written in sdram, not in flash. Where is the address of Sdram? After 4510 is powered on, it is usually set at 0x1000000, and flash is set at 0x0 address. If the program is set at 0x0 address when compiling with codewarria, the software will be loaded at a "virtual" position during debugging. This position (address) is the address of flash. MCU cannot write the program into flash, and the program becomes a ghost floating in the air. At this time, if you use disassembly, you can see that some content has deteriorated and is not your program. Do you understand why? When executing, MCU reads the content in flash, which is not your program, and the result is that it runs away. The solution is to remap (for 4510. If it is 44b0, please locate the program in the sdram segment in the codewarria compilation environment. If you need an interrupt, please write the relevant interrupt vector at 0x0 address in flash and jump to sdram), set sdram to 0x0 address, and then load the program. 5. When remap, please use the command line method in axd, the program cannot be implemented. That is: system view->command line interface. Only when the hardware address is set to be the same as the program and the program segment can be loaded into sdram, can the program be loaded. 
6. Remember these two points: the debugging program must be placed in sdram, and the sdram address must be the same as the program address. 
7. How did the address 0x8000 come from? It turns out that the address 0x0 is the interrupt vector address, which takes up dozens of bytes. Some operating systems use the part after the interrupt vector and before the address 0x8000 to do something, and Linux is one of them. Therefore, programmers use the address 0x8000 as the starting address of general programs by default. When debugging a program, you can set the program starting address to 0x8000. This address must be the address covered by sdram (I emphasize it again). When the MCU executes, it still starts from 0x0. Who moved the PC to 0x8000? It was implemented by the code added by the connector when the ads was compiled. If it is not a debugging program, but a working program, and it is to be written into the flash, the program should be located at address 0x0, not 0x8000. 
8. There is a book called "ARM Application Development System Detailed Explanation -- S3C4510B" which is very well written. I have read it 7 or 8 times. But there is one thing wrong. The book says: "For the target board introduced in this book, you can use this default address value (0x8000)." In fact, as long as it is a 4510 board, without remap, the address 0x8000 is the flash, and the program cannot be loaded. 
9. In axd, pay attention to the menu options->configure processor options. If you don't know how to use them, turn them all off. Programs with interrupts and programs that jump to address 0x0 cannot be executed, mostly due to this item. In fact, they are very useful, so I won't mention them. 
10. All the above mentioned are programs with relocation and jump. For example, a simple marquee experiment does not require interrupts or jumps. The program can be directly located in the high-bit SDRAM without remap. It can run well. 11. 
By the way, the interface package of Banyan is very good and supports ads. Don't doubt it.

(III) Startup process and REMAP based on S3C4510B system

1 Introduction to S3C4510B

S3C4510B, based on Ethernet, 16/32-bit RISC microprocessor. The chip integrates 8KB Cache/SRAM and Ethernet controller, and can be expanded with ROM, Flash, SDRAM and other storage chips.

There is no program memory inside the S3C4510B chip, and all programs are stored in the ROM and Flash that are extended outside the chip. At the beginning of the startup, the ROM or Flash containing the startup code will be mapped to the address 0x00, and the system will start running from then on. However, in actual applications, in order to improve the real-time performance of the system and speed up the execution of the code, the program is often moved to the RAM after the system starts, because the access speed of the RAM is much faster than that of the ROM, which greatly improves the performance of the system. Since the abnormal interrupt entry address in the S3C4510B chip is fixed in the 8 words starting from 0x00, the system can only reallocate the address space and map the RAM to the address 0x00, which is the reason for Remap.

There are several special registers inside the S3C4510B, which are used to implement the mapping of address space and storage media inside and outside the chip. The brief introduction of these registers is as follows:

SYSCFG: Set the starting address of special registers and the starting address of on-chip SRAM.

EXTDBWTH: Set the data line width of the chip mapped by each Bank register.

ROMCON0~ROMCON5: Set the start and end addresses of the system's on-chip expansion ROM and Flash.

DRAMCON0~DRAMCON3: Set the start and end addresses of the off-chip expansion RAM in the system.

The physical address of the special register segment in the S3C4510B chip is 0x3ff0000. For the offset address of each special register, please refer to the technical manual of the S3C4510B.

Implementation of Remap in 2S3C4510B System

The reallocation of address space is closely related to the hardware structure of the processor. Generally speaking, the address remapping mechanism in a 32-bit system can be divided into two cases: one is that the dedicated register inside the processor can complete the remap, so you only need to set the corresponding position of the remap register to 1, and the address remapping is completed by hardware logic, such as the AtmelAT91xx series; the other is that there is no dedicated remap control register, and the bank register inside the processor used to control the start and end addresses of the memory needs to be rewritten to implement the remap process. S3C4510B belongs to the second case.

2.1 Hardware system structure and address allocation

Assume that the system is built with reference to the test board provided by Samsung, where the ROM capacity is 512KB, 8-bit data bus, the address range before Remap is 0x0000000～0x0100000, and the address range after Remap is 0x1000000～0x1100000; the RAM capacity is 16MB, 32-bit data bus, the address range before Remap is 0x0100000～0x100000, and the address range after Remap is 0x0000000～0x1000000; the Flash capacity is 2MB, 16-bit data bus, and the address before and after Remap is unchanged, both 0x1100000～0x1300000. The address mapping relationship before and after Remap is shown in Figure 2.

2.2 System startup process and Remap implementation

The system address remapping should be completed during system startup. The following is the Remap startup process of S3C4510B.

① Setting of system special registers. It mainly configures the registers used to implement address space and chip internal and external storage media mapping as described above. In this system, the configuration is as follows:

SYSCFG=0x87ffff90

EXTDBWTH=0x3001

ROMCON0 = 0x01000060

ROMCON1 = 0x13044060

DRAMCON0 = 0x11004060

② Initialize the system stack. There are seven working modes in the ARM7 architecture. Different modes have different stack pointers and do not interfere with each other. Each mode corresponds to different exception interrupts. As for which mode's stack needs to be initialized, it depends on which interrupts the user uses and what types of exceptions the system needs to handle. Generally speaking, the manager (SVC) stack must be set, and if the IRQ interrupt is used, the IRQ stack must also be set. One thing to note is that in order to ensure that the program runs normally after remap, all stacks should be set in the high-end address of RAM.

③ Initialize the I/O ports, UART, timer, interrupt controller and other resources used in the system. Before initializing the exception vector table or modifying the entry address in the exception vector table, turn off all interrupts.

   ④ Initialization of the exception vector table. Write the entry address of the exception handler into the corresponding exception vector in RAM. It must be ensured that the exception vector table will never be overwritten by the code and data moved from ROM to RAM. For this reason, the exception vector table is generally defined in the high-end address in RAM.

⑤ Migration of program code and data. After Remap, RAM is mapped to the address space of 0x0000, and ROM is moved to the high-end address. To ensure that the program can run after Remap, the code and data in ROM must be moved to RAM without changing the address. This is the key to the success of Remap. There are two ways to achieve migration.

One is to directly move the entire ROM address space to RAM regardless of the actual code space size. Of course, this method is not suitable for use in real startup code, but it can be used to check whether the stack and exception interrupt settings are reasonable when doing preliminary remap tests.

Another method is more complicated. It uses the positioning information generated by the SDT linker ARMLink to move only the valid code and data segments of the RO to RAM. ARMLink links the compiled program into an ELF file. There are three output segments in the image file: RO segment, RW segment and ZI segment. These three output segments contain read-only code and a small amount of data contained in the code segment, readable and writable data, and data initialized to 0. ARMLink also generates the start and end positioning information of these three output segments: Image

RORO

Base、Image

RORO

Limit、Image

R

Base、Image

Limit、ImageLimit、Image

Linit and Image

ZIZI

Limit. You can use this positioning information in the program. Move the code and data in ROM to RAM. The implementation code is as follows:

Data definition:

BaseOfROMDCD|Image

RORO

Base|

TopOfROMDCD|Image

RORO

Limit|

BaseOfBSSDCD|Image

R

Base|

BaseOfZeroDCD|Image

ZIZI

Base|

EndOfBSSDCD|Image

ZIZI

Limit|

Source program:

; Move the program in ROM to RAM, and the remapped address remains unchanged

adrr0,ResetEntry; the starting address of the program in ROM

movr3,#(RamBaseAddr<<16);RamBaseAddr=0x100

Idrr1,BaseOfROM

Idrr2,TopOfROM

Addr1,r1,r3

Addr2,r2,r3

0

Idmiar0!,{r4-r11}

Stmiar1!,{r4-r11}

Cmpr1,r2

Bcc%B0

; Move the pre-initialized variables in the RW segment to RAM

subr1,r1,r2

subr0,r0,r1; point r0 to the end of the RO segment, that is, the beginning of the RW segment

ldrr1,BaseOfBSS

Idrr2,BaseOfZero

Addr1,r1,3

Addr2,r2,r3

1; Relative jump based on local label, PC + offset address, generates position-independent code

cmpr1,r2

ldrccr4,[r0],#4

strccr4,[r1]，#4

bcc%B1

; Then move the ZI segment to RAM and initialize it to 0

movr0,#0

Idrr2,EndOfBSS

Addr2,r2,r3

2

cmpr1,2

strccr0,[r1],#4

bcc%B2

⑥ Address remapping. The remap process in S3C4510B is actually very simple. You only need to re-set ROMCON0~ROMCON5 and DRAMCON0~DRAMCON3. In this system, you only need to re-set ROMCON0 and DRAMCON0.

source code:

;/*Memory control register reset - storage space remap address space*/

EXPORTRemapMemory

RemapMemory

movr12,r14

adrr0,RemapMem

ldmiar0,{r1-r11}

ldrr0,=ROMCON0;ROMCON0 is the starting address of the Bank register

stmiar0,{r1-r11}

blExceptionTalbeInit; interrupt vector table reinitialization

movpc,r12

RemapMem

DCD&11040060;/*ROMCON00x1000000～0x1100000*/

…

DCD&10000398;/*DRACON00x0～0x1000000*/

…

⑦ Enter the C code space and start running the main program. At this time, the code should be running in RAM.

   The above steps can be appropriately added or deleted according to actual needs. It is worth noting that the code generated by the assembly should be position-independent code, that is, the code can be mapped to different address spaces during operation, and the jump instructions are all relative jump instructions based on the PC register. The PC-based label is a label located before the target instruction or before the data definition pseudo-operation in the program. This symbol will be processed as the PC value plus or minus a numeric constant during assembly.

3. Handling of abnormal interruption

In the Remap startup code, special attention should be paid to the handling of abnormal interrupts. In S3C4510B, the entry addresses of abnormal interrupts are fixed and arranged in the order of Table 1.

Table 1 

Exception type Working mode Normal address Reset Management 0x00000000 Undefined instruction Undefined 0x00000004 Software interrupt (SWI) Management 0x00000008 Prefetch abort Abort 0x0000000 Data abort Abort 0x00000010 Reserved - 0x00000014 IRQ (interrupt) IRQ 0x00000018 FIQ (fast interrupt) FIQ 0x0000001 After the address is remapped, the entry address is mapped to RAM, and the interrupt processing code is also moved to the RAM address space. At this time, the speed of interrupt response and interrupt processing will be greatly accelerated, which will help improve the real-time performance of the entire system. The design structure of the exception interrupt vector table is shown in Figure 3.

Below is the source code of each part (taking IRQ exception interrupt as an example).

Definition of exception vector table: (When the system is initialized, the exception handling code entry address is written into the vector table in the exception)

_RAM_END_ADDREQU0x01000000; The end address of RAM after remapping

MAP(_RAM_END_ADDR - 0x100)

SYS_RST_VECTOR#4

UDF_INS_VECTOR#4

SWI_SVC_VECTOR#4

INS_ABT_VECTOR#4

DAT_ABT_VECTOR#4

RESERVED_VECTOR#4

IRQ_SVC_VECTOR#4

FIQ_SVC_VECTOR#4

Exception initialization code:

…

bIRQ_SVC_HANDLER;0x18

…

IRQ_SVC_HANDLER

SUBsp,sp,#4; Full decrement stack

STMFDsp!,{r0}

LDRr0,=IRQ_SVC_VECTOR; read the interrupt vector,

;IRQ_SVC_VECTOR=SystemrqHandle

LDRr0,[r0]

STRr0,[sp,#4]

LDMFDsp!,{r0,pc}; Jump to the exception interrupt processing code entry

Exception handling entry code:

…

SystemIrqHandler

IMPORTISR_IrqHandler

STMFDsp!,{r0-r12,lr}

BLISR_IrqHandler; Jump to the exception interrupt handler ISR_IrqHandler in C code

LDMFDsp!,{r0-r12,lr}

SUBSpc,lr,#4

…

In the above structure, regardless of whether the system performs address remapping, the exception interrupt vector can be changed dynamically at runtime, which greatly improves the flexibility of interrupt processing. The interrupt vector can point to different exception handling code entries at runtime.