A cheap "watchdog" designed using Schmitt trigger

　　This circuit can be used in single-chip microcomputer systems such as MCS-51 series. The electrical principle is shown in the attached figure.
　　
　　In the figure, a four-2-input "NAND" Schmitt trigger 74HC1320, whose gates c, gates d, gates b, C3, C4, R4, R5, D3, D2, etc., form a "watchdog"
　　
　　circuit. Unlike the familiar "watchdog" circuit, there is no oscillation circuit in between. In the figure, gates c and C3 play an isolation role. The input end of gate c can be connected to an I/O pin that often changes in the main loop of the system program (because it is a standard CMOS high-impedance input, it will not affect the function of the I/O pin), or an I/O pin can be specially set for it, such as P3.7 port. Just add an instruction to negate the port (such as CPLP3.7) in the main loop program - the port outputs a high level in a small loop, and outputs a low level in another loop... In this way, the output end ③ of gate c will change continuously, and the output end ⑥ of gate d will also change accordingly. When the ⑥ pin is at a high level, the capacitor C4 is charged through R5. When the ⑥ pin is at a low level, C4 is quickly discharged through the diode D3. Therefore, as long as the main loop of the system program runs normally, the output of the I/O port keeps changing, that is, the ⑥ pin of gate d keeps changing, C4 cannot be charged and is always at a low level, which is added to gate b, so that the ⑩ pin of gate b outputs a high level. In this way, since D1 and D2 are blocked, gate b has no effect on the entire circuit, and the entire system remains in normal operation.
　　
　　If the system is interfered and freezes or the program runs away, the main loop cannot run normally, and the I/O port (P3.7) no longer changes. At this time, the input end of gate c, regardless of whether it stays at a high level or a low level, due to the isolation of capacitor C3, the input ends of gate d, ④ and ⑤, are pulled down by resistor R4, and its ⑥ pin outputs a constant high level. C4 is charged through R5, and after about 500ms, the gate b (11) pin outputs a low level. On the one hand, C1 is discharged quickly through D1, making the ⑩ pin of gate a low level, and the ⑧ pin of gate a outputs high level, causing the CPU to reset. On the other hand, C4 is discharged through D2 and R3. When C4 is discharged to the VL threshold level, gate b flips, and its 11 pin outputs high level, blocking D1 and D2. In this way, capacitors C1 and C4 start to charge through R1 and R5 respectively. Since the charging and discharging time constants of R1 and C1 are only a fraction of R5 and C4, gate a flips first, and its ⑧ pin outputs low level. After the CPU is reset, it starts to operate normally again. Once the main loop runs normally, the input of gate c keeps changing, and the output of gate b keeps changing, and C4 cannot be charged again... In the figure, gate a, resistors R1 and R2, capacitors C1 and C2, and voltage-stabilizing diode DW form a voltage monitoring circuit. R1 and C1 on the ⑩ pin of gate a are mainly used for "power-on automatic reset", that is, in the initial stage of system power-on, the ⑩ pin of gate a is at a low level, so that its ⑧ pin outputs a high-level reset pulse, and the CPU is reset. C2, R2, and DW on the 9th pin of gate a play a "power-off protection role". At the moment of power-on, due to the presence of C2, the 9th pin is at a high level. When the power supply voltage is stable, due to the presence of the 2.4V voltage-stabilizing diode DW, the potential of the 9th pin is clamped at VDD-2.4=5-2.4=2.6V. According to the characteristics of the Schmitt trigger, the 9th pin is still "kept at a high level" and will not affect the original state of gate a. When the system power is off or undervoltage, such as VDD drops to 4V, the potential of the 9th pin is VDD-2.4=4-2.4=1.6V, which is lower than the VL threshold voltage. At this time, gate a flips, and its 8th pin outputs a high level, putting the CPU in a reset state, avoiding the system's erroneous operation during power-off and undervoltage. The reset protection is not revoked until the power returns to normal, and the CPU starts to operate normally.