Research on ARM interrupt processing

      The commonly used RISC processor in embedded systems is the ARM core, which has the characteristics of small size, low power consumption, low cost and high cost performance. However, no matter which model of ARM processor is used, and whether there is an operating system in the embedded system, interrupt processing, especially IRQ interrupt, is always necessary, and the core issue of interrupt processing is context preservation. Whether the context can be saved safely and efficiently will affect the performance and stability of an embedded system. The author analyzes and summarizes the context preservation technology of ordinary interrupt processing, task switching interrupt processing, re-entry interrupt processing and priority-based re-entry interrupt processing of ARM processors. To ensure the correctness of the theory, the core program code has been tested experimentally.

　　1 Introduction to System Interrupt Processing

　　There are two main types of interrupts in ARM processors: IRQ normal interrupts and FIQ fast interrupts. Fast interrupts are essentially not much different from normal interrupts, and they have many similarities in processing mechanisms. IRQ interrupts are the most frequent and have the greatest impact on system performance, so their research and processing are the most valuable.
 

　　The following is a brief introduction to the working process of the ARM processor when an IRQ exception occurs. When an IRQ interrupt occurs, the hardware of the ARM processor automatically performs the following tasks:

　　①Save the CPSR value of the interrupted task mode to the SPSR register in the IRQ mode;

　　②Save the PC value of the interrupted task mode to the LR register in the IRQ mode;

　　③ Automatically switch the mode to IRQ mode, and set bit7 in CPSR to 1 to disable subsequent IRQ interrupts;

　　④PC is assigned the address value of 0x18, and the program will start executing from 0x18. Combined with Figure 1, we can better understand the working process of the ARM interrupt processing mechanism.

　　2 Normal interrupt processing

　　Some ARM embedded systems may have relatively low requirements for interrupts, that is, after an interrupt occurs, the corresponding interrupt source is first queried, then the interrupt service is performed, and finally the program is returned from the interrupt service program to the interrupted location to continue running. How to ensure safe and efficient interrupt processing in such a simple application? "Safety" means that the context is intactly saved and not destroyed when an interrupt occurs, and "efficiency" means saving as few registers as possible (of course, it is based on safety). As shown in Figure 1, in ordinary interrupt processing, interrupt service can run in IRQ mode. According to the calling rules of ATPCS, the ARM compiler saves the R4~R11 registers in the subroutine call, so there is no need to save them again. Then the remaining registers must be saved to prevent them from being destroyed after returning from the interrupt service program. The processing code can be written in assembly language and C language.

　　First, it is assumed that the IRQ stack has been correctly established in the initialization code.

　　; All services will be interrupted at the same time to improve efficiency

　　LDMFD SP!, {R0-R3, R12, R14}; Restore context

　　There is no need to save the SPSR in the above save context, because in a non-nested interrupt handler, it will not be destroyed by any order of interrupts.

　　If you write the handler in C language, you can use the keyword IRQ to tell the compiler to do the following:

　　① Save the destroyed registers specified by ATPCS;

　　②Save registers used in other interrupt handlers;

　　③At the same time, (LR-4) is assigned to the program counter PC to realize the return of the interrupt program and restore the contents of the CPSR register.

　　The C language program for ordinary interrupt processing can be written in the following format:

　　It can be seen that whether it is written in C language or assembly language, their working principles are the same. Figure 2 shows the schematic diagram of ARM register saving during normal interrupt processing (the dotted line is stack push and save, and the solid line is stack pop and restore). The figure corresponds to the steps of program processing, which can help understand the process of saving the processor context.

3 Task Switching

　　In embedded systems with operating systems, the occurrence of an interrupt requires saving the contents of all registers to the task stack. This is not based on safety considerations because the interrupt may cause a task switch. When a task switch occurs, the values ​​of all task registers must be saved to the task stack. The context of the next task will be restored from the task stack to the processor registers. The following is an analysis of this issue and the implementation program code is given. From the preservation of interrupt processing registers in Figure 1, it can be seen that after the interrupt occurs, the values ​​of the task's CPSR and PC registers are in the SPSR and LR of the IRQ mode, so it cannot be simply switched to the task running mode, otherwise the CPSR and PC will not be visible when the interrupted task returns (because they are saved in the dedicated registers of the IRQ mode and cannot be operated in other modes). At this time, you can consider setting some variable areas as a medium to transfer them to the stack of the task running mode.

　　It is assumed that the task switch is executed in SVC mode. Combining the above analysis, we can have the schematic diagram of the save task switch shown in Figure 3 (the dotted line is the stack push save, the solid line is the stack pop restore; LR_Frame and SPSR_Frame are variable areas).

　　Combined with the steps in the task switching interrupt processing in Figure 3, the corresponding interrupt processing program can be written in assembly language:

　　4 Reentrancy Interrupts

　　If you want to respond to other interrupt requests while processing an interrupt to shorten the interrupt latency, you must design a reentrant interrupt. Reentrant interrupts are a way to handle multiple interrupts, but they also bring new problems. In IRQ interrupt mode, if the IRQ interrupt is directly re-enabled, the return address of the subroutine is saved in LR_irq because a BL instruction is executed, and an interrupt occurs during this time. The new interrupt will load its return address into LR_irq, and the return address of the old interrupt subroutine will be overwritten, causing system disorder. This situation cannot be solved by pushing LR_irq onto the stack, such as the program statement:

　　However, the possibility of an interrupt occurring before LR is saved cannot be ruled out. To solve the above problem of LR_irq being destroyed, the processor mode must be switched, and the most common mode is to switch to SVC processing mode. In SVC mode, the return address is saved in LR_SVC when a subroutine is called through BL. At this time, a new interrupt occurs (because it saves the return address to LR_irq instead of LR_SVC), and the subroutine return address in the old interrupt will not be destroyed. With the above principle analysis, the idea of ​​writing reentrant interrupt code is clear. However, in order to ensure the efficiency of processing, interrupts are allowed as early as possible to shorten the delay. After saving LR_irq and SPSR_irq, switch to SVC mode immediately and re-enable interrupts, as shown in Figure 4 (the dotted line is stack push save, and the solid line is stack pop restore).

　　Combined with the processing steps in Figure 4, the assembly language program for reentrant interrupt processing can be written more clearly: