8051 MCU port structure—P0 port

　　The 8051 microcontroller has four 8-bit parallel I/O ports, denoted as P0, P1, P2 and P3. Each port is an 8-bit quasi-bidirectional port, occupying a total of 32 pins. Each I/O line can be used independently as input or output.

　　Each port includes a latch, an output driver, and can latch data for output and buffer data for input. In a system without external memory, each bit of these four ports can be used as a quasi-bidirectional general-purpose I/O port.

　　In a system with off-chip extended memory, port P2 sends out the high 8-bit address, and port P0 is a bidirectional bus that sends out the low 8-bit address and data input/output respectively. The circuit design of the four I/O ports of the 8051 microcontroller is very clever. Being familiar with the I/O port logic circuit is not only conducive to the correct and reasonable use of the port, but also will be inspiring for the design of the microcontroller peripheral logic circuit.

　　Each bit of the P0 port is composed of an output latch, two three-state input buffers , an output drive circuit, a control circuit and gate, an inverter , and a MUX control. When the CPU makes the control line C=0, the digital control switch MUX is downward, and the P0 port is a general I/O port; when C=1, the switch is pulled to the output of the inverter, and the port is used for the address/data bus in a time-sharing manner.

　　Let's first look at the use of P0 as an I/O port:

　　When the system composed of 8051 has no external memory, the CPU reads and writes the on-chip memory and I/O port. When executing the MOV instruction, or executing the MOVC instruction under the condition of EA=1, the hardware automatically makes the control line C=0, the switch MUX turns downward, and its output stage T2 is connected to the reverse end of the latch Q; at the same time, because the AND gate output is 0, the pull-up field effect transistor T1 in the output stage is in the cut-off state, so the output stage is an open-drain circuit. At this time, the P0 port can be used as a general I/O port.

　　Generally, I/O ports have two operations: input and output. Let's first look at the case where P0 is used as an output port. When the CPU executes an output instruction, a write pulse is added to the D latch, so that the data connected to the internal bus is inverted and appears on Q. If the data at the D end is 0, the data at the inverted end is 1, and the field effect transistor T2 is turned on and outputs 0. At this time, the pin is pulled high the pull-up resistor , so that the signal 1 on the data bus is accurately sent to the pin.

　　8051 has several output instructions that are particularly powerful and belong to the "read-modify-write" instructions. For example, the process of executing an ANL P0, A instruction is: instead of directly reading the data on the pin, it reads the data in the latch at the D end of the P0 port. When the "read latch" signal is valid, the tri-state buffer 1 is turned on, and the internal bus of the Q end data and the data in the accumulator A are "logically ANDed" and the result is sent back to the latch of the P0 port. At this time, the inside of the latch is consistent with the pin.

　　The following is an analysis of the case where port P0 is used as an input port, and buffer 2 is used by the CPU to directly read port data. When an instruction input from the port is executed, the "read pin" pulse turns on the tri-state buffer, so that the data on the port is read into the internal bus through buffer 2. This type of operation is implemented by data transfer instructions. When reading port pin data, since the output drive field effect transistor T2 is connected to the pin in parallel, if T2 is turned on, the input high level will be pulled to a low level, resulting in misreading. Therefore, before the port performs an input operation, "1" should be written to the port latch first, that is, the latch Q is reversed to 0, because the control line C = 0, so T1 and T2 are cut off, the pin is in a suspended state, and can be used as a high impedance input.

　　Next, let's look at the situation when the control line C=0, and the P0 port is used as the address/data bus. When the 8031 ​​external memory system is composed, the CPU reads and writes to the external memory, the CPU reads and writes to the external memory, that is, executes the MOVX instruction, or executes the MOVC instruction under the condition of EA=0, the internal hardware automatically makes the control line C=1, and the switch MUX is turned to the output end of inverter 3. At this time, P0 can be used as the address/data bus respectively, and it is divided into two situations.

　　1. Port P0 can be used as an output address/data bus. In an expansion system, one method is to input the lower 8 bits of address or data information via the pin of port P0.

　　2. Another situation is that data is input from port P0. In this case, when the "read pin" signal is valid, the input buffer is opened to allow data to enter the internal bus.

　　To sum up, P0 can be used as a general I/O port or as an address/data bus.