Design of power-off protection scheme for embedded systems

　　In the process of embedded system design, the power-off protection of the system is increasingly valued. The method introduced in this paper is implemented on an embedded platform built with ARM7 series chip S3C4510B and μClinux. The basic idea of ​​the entire power-off protection is to generate power-off signals, capture power-off signals and process power-off signals. The specific implementation of this process is emphasized.

　　The purpose of the system power-off protection design is to adopt a mechanism to ensure the certainty of the system operation status and the integrity of the recorded data when the system loses power unexpectedly; when the system power is restored, the field data can be restored in time to avoid confusion in the application system. We know that embedded operating systems are increasingly used in the design and development of embedded systems. Due to the introduction of operating systems, data reading and writing are often completed through files rather than directly operating on the storage unit address. When operating data in the file reading and writing mode, data is often temporarily stored in volatile storage space, such as SDRAM, during the operation of the program. Once the system loses power unexpectedly, these data are often lost. Therefore, when the system loses power unexpectedly, certain measures must be taken to protect the system from power failure to avoid confusion in the system. In general, the main idea of ​​the power-off protection program is to generate power-off signals, capture power-off signals, process power-off signals and data, and restore the field status.

　　If the operating system is not introduced, and the data is directly operated on the storage unit, the amount of data each operation is small, and the power-off protection can be performed by interrupt service; while the data is operated by file, the amount of data is generally large, so the power-off protection based on interrupt service is no longer reliable. The object of this paper is the power-off protection in the design process of a more complex embedded system based on an operating system.

　　1 System basis for implementing power-off protection scheme

　　Power-off protection is implemented on the basis of ARM hardware platform and μClinux embedded operating system.

　　The ARM7 series of microprocessors support eight types of interrupt processing. The external interrupt request will be responded to by the processor when the external interrupt pin is valid (usually low level) and the relevant bit of the program status register (i.e. the I control bit of CPSR) is set to enable. After the response, the processor enters the interrupt working mode, and the PC is loaded into the interrupt vector 0x00000018. The interrupt service program population address is stored in this address unit, and the interrupt service program can be executed. In the power-off protection scheme, the interrupt service program is very simple, which is to set the global variable indicating power-off. This can shorten the program execution time.

　　Flash memory is a memory that can be electrically erased and written in the system without losing information after power failure. It has the characteristics of low power consumption, large capacity, in-system programming (burning) and erasing of the entire chip or sectors, and the chip can be operated by internal embedded algorithms, so it has been widely used in various embedded systems. As a non-volatile memory. Flash is usually used in the system to store program code, constant tables, and some user data that needs to be saved after the system power is off. Commonly used Flash has a data width of 8 or 16 bits, and the programming voltage is a single 3.3V.
 

 　　Compared with Flash memory, SDRAM does not have the characteristic of retaining data when power is off, but its access speed is much higher than Flash memory, and it has read/write properties. Therefore, SDRAM is mainly used as the program running space, data and stack area in the system. When the system starts, the CPU first reads the startup code from the reset address 0x0. After completing the system initialization, the program code should generally be transferred to SDRAM to run in order to increase the system's running speed. At the same time, the system and user stacks and running data are also placed in SDRAM. The storage unit of SDRAM can be understood as a capacitor, which always tends to discharge. In order to avoid data loss, it must be refreshed (charged) regularly. Therefore, to use SDRAM in the system, it is required that the microprocessor has a refresh control logic, or a refresh control logic circuit is added to the system. In particular, after the system loses power, an effective mechanism must be adopted to ensure that the data in SDRAM is written into F1ash.

　　2 Hardware design based on power-off protection scheme

　　Figure 1 is a typical embedded system hardware design. The system's microprocessor uses S3c4510B, which is based on the ARM7 architecture. SDRAM is a volatile memory that serves as a program running space, similar to the memory of a PC; Flash is a non-volatile program storage space. Data during program execution is often cached in SDRAM and must be written to Flash when the system loses power.

　　In the system, 5V and 3.3V DC regulated power supplies are required. Among them, S3C4510B and some peripheral devices require 3.3V power supply, and some other devices require 5V power supply. In order to simplify the design of the system power supply circuit, the input voltage of the entire system is required to be a high-quality 5V DC regulated power supply. Different from the general power supply circuit design, the power supply circuit design process of this system adds the design of power-off protection. The system power supply circuit including this design is shown in Figure 2.

　　In addition to providing 5v and 3.3v power, this power circuit also provides delay and warning functions for system power-off protection. The system power-off protection mechanism can be realized through software cooperation. Under normal circumstances, the power supply circuit 1 supplies power to the entire system. When the system loses power due to unexpected reasons, due to the reduction of the input comparison voltage, the output voltage of the MAX809 module is reversed to provide the system with a power-off interrupt warning signal, and the interrupt request is generated through the external interrupt pin XREQ0; at the same time, the power supply circuit 2 starts to be enabled. Through the discharge of large capacitors C3 and c4, a supply voltage is continuously provided to the system to support the completion of the power-off interrupt service program. Power supply circuit 2 only supplies power to the minimum system, and does not supply power to peripheral components with high power consumption. In this way, the power supply time for the minimum system is long enough to complete the protection operation of sensitive data.

　　Through software calculation, the minimum system working time for capacitor discharge is between 0.5 and 4.5 seconds. This calculation method is very simple. Write a power-off interrupt service subroutine, which only continuously performs time refresh operations. Similarly, the software can be used to determine that 2 to 3 MB is erased to the Flash during this period. It can be seen that under the use of this hardware system, the system power-off protection can be reliably guaranteed.

　　3 Implementation of power-off signal processing software method

　　In μClinux system, there are two ways to capture power-off signal. One is to use system call, that is, void(*signal(intslg, void(*func)(int)))(int). This function can arrange the execution function for a specific interrupt signal, and pass it with the parameter func. In μCllnux, there are 31 system interrupt signals, among which the power-off signal is SIGPWR. Assuming that the power-off interrupt service handler is void interrupt-service(int), the way to associate the interrupt service with the signal is: signal(SIGPWR, interrupt_service). This method makes full use of system calls and is simple to implement. This mechanism was also used in the early stage of the power-off protection scheme design. However, it turns out that this mechanism is not reliable. The reason is that the mechanism for generating and managing signals in the Linux kernel is not perfect, and there may be signal loss. By consulting relevant information about Unix or L1nux, it can be found that this situation is also common in some other versions of Linux and Unix.

　　Another way is to use a waiting process to start a process that specifically waits for an interrupt signal. The main program divides its own process plan into several atomic operations according to the different data operation objects. The so-called atomic operation means that the designated program block is either fully executed or not executed. Each operation corresponds to a unique status flag. Before each atomic operation, the main process will read the interrupt signal through pipeline communication. If an interrupt signal is generated, the main process first saves the status flag, then writes the relevant data to the Flash and exits. After the power is restored, the main process first determines the system recovery plan based on the flag word. Figure 3 implements this process in the form of a flowchart.

　　Conclusion

　　The tax control cash register designed based on this scheme has complete power-off protection function in actual operation. The application object of this power-off protection design method is the embedded system built based on ARM and μClinux, which has a typical representative significance in the development of 32-bit embedded systems. Therefore, it has promotion value in embedded system design.