ATmega 16 MCU USART related registers (10)

Full-duplex operation (independent serial receive and transmit registers)
Asynchronous or synchronous operation
Synchronous operation with clock provided by the master or slave
High-precision baud rate generator
Supports 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Parity operation supported by hardware
Data overrun detection
Frame error detection
Noise filtering, including wrong start bit detection, and digital low-pass filter
Three independent interrupts: transmit end interrupt, transmit data register empty interrupt, and receive end interrupt
Multi-processor communication mode
Double-speed asynchronous communication mode

1.UDR——USART I/O Data Register

The USART Transmit Data Buffer Register and the USART Receive Data Buffer Register share the same I/O address, called the USART Data Register or UDR. Writing data to the UDR actually operates on the Transmit Data Buffer Register (TXB), and reading the UDR actually returns the contents of the Receive Data Buffer Register (RXB). In 5, 6, and 7-bit word length modes, unused high bits are ignored by the transmitter and set to 0 by the receiver. The transmit buffer can only be written if the UDRE flag in the UCSRA register is set. If UDRE is not set, data written to the UDR is ignored by the USART transmitter. When data is written to the transmit buffer, the transmitter loads the data into the transmit shift register if the shift register is empty. The data is then output serially on the TxD pin. The
receive buffer includes a two-level FIFO, which changes its state once the receive buffer is addressed. Therefore, do not use read-modify-write instructions (SBI and CBI) on this memory location. Be careful when using bit query instructions (SBIC and SBIS) as these may also change the state of the FIFO.
2.UCSRA——USART Control and Status Register A

          RXC TXC UDRE FE DOR PE U2X MPCM

Bit 7 - RXC: USART receive complete
RXC is set when there is unread data in the receive buffer, otherwise it is cleared. When the receiver is disabled, the receive buffer is refreshed, causing RXC to be cleared. The RXC flag can be used to generate a receive complete interrupt (see the description of the RXCIE bit).
Bit 6 - TXC: USART transmit complete
The data in the transmit shift buffer is sent out, and TXC is set when the transmit buffer (UDR) is empty. The TXC flag is automatically cleared when the transmit complete interrupt is executed, and it can also be cleared by writing 1. The TXC flag can be used to generate a transmit complete interrupt (see the description of the TXCIE bit).
Bit 5 - UDRE: USART data register empty
The UDRE flag indicates whether the transmit buffer (UDR) is ready to receive new data. UDRE is 1, indicating that the buffer is empty and ready for data reception. The UDRE flag can be used to generate a data register empty interrupt (see the description of the UDRIE bit). UDRE is set after reset, indicating that the transmitter is ready.
Bit 4 - FE: Framing Error
If the next character received in the receive buffer has a framing error, that is, the first stop bit of the next character in the receive buffer is 0, then FE is set. This bit is valid until the receive buffer (UDR) is read. When the received stop bit is 1, the FE flag is 0. When writing to UCSRA, this bit should be written as 0.
Bit 3 - DOR: Data Overflow
DOR is set when data overflow occurs. When the receive buffer is full (contains two data), the receive shift register has data again, and if a new start bit is detected at this time, a data overflow occurs. This bit is valid until the receive buffer (UDR) is read. When writing to UCSRA, this bit should be written as 0.
Bit 2 - PE: Parity Error
UPE is set when parity is enabled (UPM1=1) and the next character received in the receive buffer has a parity error. This bit is valid until the receive buffer (UDR) is read. When writing to UCSRA, this bit should be written as 0.
Bit 1 – U2X: Double Speed ​​Transmit
This bit only affects asynchronous operation. Clear this bit when using synchronous operation. Setting this bit to 1 reduces the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication mode.
Bit 0 – MPCM: Multiprocessor Communication Mode
Setting this bit enables multiprocessor communication mode. When MPCM is set, any incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is not affected by the MPCM setting.

3.UCSRB——USART Control and Status Register B

            RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8

Bit 7 - RXCIE: Receive end interrupt enable
When set, the RXC interrupt is enabled. When RXCIE is 1, the global interrupt flag SREG is set, and the RXC in the UCSRA register is also 1, a USART receive end interrupt can be generated.

Bit 6 - TXCIE: Transmit End Interrupt Enable
When set, the TXC interrupt is enabled. When TXCIE is 1, the global interrupt flag bit SREG is set, and the TXC in the UCSRA register is also 1, a USART transmit end interrupt can be generated.
Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
When set, the UDRE interrupt is enabled. When UDRIE is 1, the global interrupt flag bit SREG is set, and the UDRE in the UCSRA register is also 1, a USART data register empty interrupt can be generated.
Bit 4 - RXEN: Receive Enable
When set, the USART receiver is enabled. The general port function of the RxD pin is replaced by the USART function. Disabling the receiver will refresh the receive buffer and invalidate the FE, DOR, and PE flags.
Bit 3 - TXEN: Transmit Enable
When set, the USART transmitter is enabled. The general port function of the TxD pin is replaced by the USART function. After TXEN is cleared, the transmitter can only be truly disabled after all data transmission is completed, that is, there is no data to be transmitted in the transmit shift register and the transmit buffer register. After the transmitter is disabled, the TxD pin resumes its general purpose I/O function.
Bit 2 - UCSZ2: Character Length
UCSZ2 is combined with UCSZ1:0 of ​​the UCSRC register to set the number of data bits (character length) contained in the data frame.
Bit 1 - RXB8: Receive data bit 8
When operating on a 9-bit serial frame, RXB8 is the 9th data bit. RXB8 must be read before reading the low-order data contained in the UDR.
Bit 0 - TXB8: Transmit data bit 8
When operating on a 9-bit serial frame, TXB8 is the 9th data bit. Write to it before writing to the UDR.

4.UCSRC——USART Control and Status Register C

                 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL

The UCSRC register shares the same I/O address as the UBRRH register.

Bit 7 - URSEL: Register Select
This bit is used to select access to the UCSRC register or the UBRRH register. This bit is 1 when reading UCSRC; URSEL is 1 when writing UCSRC.
Bit 6 - UMSEL: USART Mode Select
This bit is used to select synchronous or asynchronous operation mode.

            UMSEL mode
                0 Asynchronous operation
                1 Synchronous operation

Bits 5:4 - UPM[1:0]: Parity Mode
These two bits set the parity mode and enable parity. If parity is enabled, the transmitter will automatically generate and send parity bits when sending data. For each received data, the receiver will generate a parity value and compare it with the value set in UPM0. If there is a mismatch, PE in UCSRA is set.

        UPM1 UPM0 Parity mode
           0 0 Disable
           0 1 Reserved
           1 0 Even parity
           1 1 Odd parity

Bit 3 - USBS: Stop bit selection
This bit can be used to set the number of stop bits. The receiver ignores the setting of this bit.

                           USBS stop bit number
                               0 1
                               1 2

Bit 2:1 - UCSZ[1:0]: Character length
UCSZ1:0 combined with UCSZ2 of the UCSRB register can set the number of data bits (character length) contained in the data frame.

                  UCSZ2 UCSZ1 UCSZ0 Character length
                      0 0 0 5 bits
                      0 0 1 6 bits
                      0 1 0 7 bits
                      0 1 1 8 bits
                      1 0 0 Reserved
                      1 0 1 Reserved
                      1 1 0 Reserved
                      1 1 1 9 bits

Bit 0 - UCPOL: Clock polarity
This bit is used only in synchronous mode. When using asynchronous mode, clear this bit. UCPOL sets the relationship between the output data change and the input data sampling and the synchronous clock XCK.

       UCPOL Change of transmit data (output of TxD pin) Sampling of receive data (input of RxD pin)
           0 XCK rising edge XCK falling edge
           1 XCK falling edge XCK rising edge

5.UBRRL and UBRRH - USART baud rate register

The UCSRC register shares the same I/O address as the UBRRH register.

Bit 15 - URSEL: Register Select
This bit selects access to the UCSRC register or the UBRRH register. This bit is 0 when reading UBRRH; URSEL is 0 when writing UBRRH.

Bits 14:12 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, write UBRRH to clear these bits.
Bits 11:0 - UBRR1[1:0]: USART Baud Rate Register
This 12-bit register contains the USART baud rate information. UBRRH contains the upper 4 bits of the USART baud rate and UBRRL contains the lower 8 bits. A change in the baud rate will cause data transfers in progress to be corrupted. Writing UBRRL will immediately update the baud rate divider.