Preface

In the C run time library, memcpy is an important function that has a significant impact on the performance of application software. The development of ARM chips to the Cortex-A8[1][2] architecture has not only greatly improved the frequency, but also greatly improved the architectural design. The added NEON instructions are similar to the original MMX instructions under the X86 platform and are designed for multimedia. However, because these instructions can process 64-bit data at a time, they are also helpful for improving the performance of the memcpy function. This article mainly tests various memcpy implementations using the NEON[2] instruction, explores the impact of the NEON instruction and preload instruction on performance, and the changing trend of these impacts after chip optimization and process improvement. At the same time, it is hoped that chip designers can give an explanation based on the understanding of software implementation, so as to guide the direction of further improving performance.

Platform Introduction

The test platform for this time is derived from the Cortex-A8 platform that the author encountered in his work project. See the list below:

i.MX5 family

For an introduction to the i.MX5 family, see [6][7]. The i.MX535 can run at two frequencies: 800MHZ and 1000MHZ.

Snapdragon family

For an introduction to Snapdragon, see [8][9][10]. The msm7x30 can run at two frequencies: 800MHZ and 1000MHZ. In addition, the Snapdragon cache is special in that it is 128-bit wide (NEON), 128-byte / line. In the standard Cortex-A8, this value is 64-bit wide (NEON), 64-byte / line. This has a significant impact on performance.

s5pc family

The s5pc family reference platform can be found in [11].

omap3 family

For the omap3 family reference platform, see [12][13][14].

Introduction to memcpy implementation

There are three versions of memcpy implementation on the ARM platform:

ARM's document [4] has a good description of the implementation of memcpy. Others [5][19][20] have further elaborated on the implementation principles and techniques. A brief description is as follows:

C language version

The C language version is mainly for comparison. Two implementations are used:

It is worth noting that the compiler will not actively insert pld instructions because the compiler cannot determine the application's memory access pattern.

ARM assembly version

The ARM assembly version is also mainly for comparison. Two implementations are used:

NEON assembly version

The NEON assembly version uses four implementations:

Test plan introduction

The test plan is very simple. It refers to the implementation of the moving memory tester [21]. The execution steps are as follows:

The block size mentioned above = 2^n ( 7 <= n <= 23 ).

In addition, this test program runs in the openembedded-gpe software system. QualComm / Samsung hardware platforms only provide Android software systems, and it is a bit troublesome to switch to the GPE system, so the chroot method is used for testing. Regardless of the software platform, after entering the graphics system, wait for the black screen and then test.

The following table shows the statistics of the operating environment.

The following table shows the statistics of the test items.

Note 1: Because the i.MX53 EVK board malfunctioned, all no pld test items could not be tested.

Note 2: After opening the preload engine for omap3430, the test generated an illegal instruction error and failed to test the ple test items.

Note 3: It is a bit troublesome to replace the Snapdragon kernel, and the test items of ple cannot be tested.

Test results and analysis

The following chart is limited by the page size and cannot show the details well. The specific data and large picture can be viewed in the data sheet document.

Performance of various implementations on various hardware platforms

imx51 800MHZ

imx53 1000MHZ

imx53 800MHZ

msm7230 1000MHZ

msm7230 800MHZ

msm8250 1000MHZ

omap3430 550MHZ

omap3730 1000MHZ

s5pc100 665MHZ

s5pc110 1000MHZ

1. summary

Performance of various hardware platforms under small/big block size

Since the block size can be divided into two types: fit in cache and out of cache, two profiles are made for comparative analysis.

Realization of Möns Rullgörd

Because M?ns Rullg?rd's implementation is the simplest, with only a loop body and no other judgment code, it can be considered as an implementation that reflects the speed limit of the platform.

ARM Implementation

NEON Implementation

summary

Practical ARM/NEON implementation on various hardware platforms

By comparing the performance of the same implementation on different hardware platforms and combining it with the charts in the previous section, we can evaluate the average performance, or adaptability, of an implementation.

ARM Implementation

NEON Implementation

summary

Summarize

Further testing

Because in the Cortex-A8 series chips, the NEON module is required. In the Cortex-A9 series chips, the NEON module is optional. Because the NEON module affects the die size, thus affecting power consumption and cost. Therefore, some Cortex-A9 chips, such as Nvidia Tegra250, do not have a NEON module. So what impact will the presence or absence of a NEON module have on software performance?