ARM key registers

The abbreviations in the figure are as follows:

R：Register; register
PC：Program Counter; Program Counter
CPSR: Current Program Status Register; Current Program Status Register
SPSR: Saved Program Status Register; Saved Program Status Register
SP：Stack Pointer; data stack pointer
LR: Link Register; connection register
SB: Static Base Register
SL: Data stack limit pointer
FP: Frame Pointer
IP: Intra-Procedure-call Scratch Register; internal program call scratch register

ARM has 37 registers in total, which can work in 7 different modes. The following is a classification explanation based on the above figure:

Ungrouped registers r0-r7 are shared by all modes, 8 in total.
In the grouped registers r8-r12, the fast interrupt mode has its own set of registers, which are shared by other modes, so there are 10 of them.
Among the grouped registers, r13 and r14 are shared by user mode and system mode, while other modes have one group each, so there are 2*7 - 2 = 12 in total.
r15 and CPSR are shared, for a total of 2; SPSR has one in each mode except user mode and system mode, for a total of 5.

So the total is 8+10+12+2+5 = 37. The corresponding assembly names indicate their common usage conventions.

1. PC (Program Counter) = EIP in Windows

Analysis: 
The programs (instruction sequences) to be executed by the processor are pre-stored in the computer's memory in the form of binary code sequences. The processor fetches these codes one by one into 
the processor, decodes them, and executes them to complete the execution of the entire program. In order to ensure that the program can be executed continuously, the CPU must 
have  some means to determine the address of the next instruction fetch. The program counter (PC) plays this role, so it is usually called the "instruction counter"
. The CPU always fetches, decodes, and executes the instruction sequence according to the direction of the PC. In other words, it is the PC that ultimately determines the direction of program operation. Therefore, 
the program counter (PC) belongs to the category of special function registers and cannot be freely used to store other operation data.

Before the program starts executing, the starting address of the program instruction sequence, that is, the address of the memory unit where the first instruction of the program is located, is sent to the PC, and the CPU 
reads the first instruction from the memory (fetches instructions) according to the instructions of the PC. When executing instructions, the CPU automatically modifies the content of the PC, that is, the PC increases by an 
amount for each instruction executed, which is equal to the number of bytes contained in the instruction (the number of instruction bytes), so that the PC always points to the address of the next instruction to be fetched. Since most instructions 
are  executed in sequence, the process of modifying the PC is usually just a simple addition of the "number of instruction bytes" to the PC.
When the program is transferred, the final result of the execution of the transfer instruction is to change the value of the PC, and this PC value is the target address to be transferred. The processor always 
fetches, decodes, and executes instructions according to the PC, thereby realizing program transfer.

2. Stack pointer register SP (register R13)

In ARM processors, register R13 is usually used as a stack pointer (SP). ARM processors have a total of 6 stack pointers (SP) for different modes, of which 
user mode and system mode share one SP, and each exception mode has its own dedicated R13 register (SP). They usually point to the 
dedicated  , that is, the ARM processor allows user programs to have six different stack spaces, and R13 in the ARM processor is used as SP. When the stack is not used,
R13 can also be used as a general data register.

Since each operating mode of the processor has its own independent physical register R13, in the initialization part of the user application, it is generally necessary to initialize R13 in each 
mode  to point to the stack space of the operating mode. In this way, when the program enters the exception mode, the registers that need to be protected can be placed in
the stack pointed to by R13, and when the program returns from the exception mode, it is restored from the corresponding stack. This method can ensure the normal execution of the program after the exception occurs 
.

3. R14 is called the subroutine link register LR (Link Register)

When executing the subroutine call instruction (BL), R14 can get 
the backup  . In each operation mode, R14 can be used to save the return address of the subroutine. When the subroutine is called with the BL or BLX instruction, the current value of PC is given to
R14. After the subroutine is executed, the value of R14 is returned to PC to complete the call and return of the subroutine. The above description can be completed with instructions. 
Execute any of the following instructions: 
MOV PC,LR 
BX LR 
Use the following instructions at the subroutine entry to store R14 in the stack: 
STMFD SP! ,{,LR} 
Correspondingly, the following instructions can be used to complete the subroutine return: 
LDMFD SP! ,{,PC} 
R14 can also be used as a general register.

4. PSR Register

Condition Code Flags 
N, Z, C, and V are condition code flags. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether an instruction 
is executed. 
In ARM state, most instructions are conditionally executed. 
In Thumb state, only branch instructions are conditionally executed.

N Negative Set if the result is negative When performing operations on signed numbers represented by two's complement, N = 1 indicates that the result of the operation is negative; N = 0 indicates that the result of the operation is positive or zero. 
Z Zero Set if the result is zero Z = 1 indicates that the result of the operation is zero; Z = 0 indicates that the result of the operation is not zero. 
C Carry Set if a carry occurs There are 4 ways to affect the value of C: 
l Addition operation: When the result of the operation produces a carry (unsigned overflow), C = 1, otherwise C = 0. 
2 Subtraction operation (including comparison instruction CMP): When a borrow occurs during the operation (unsigned overflow), C = 0, otherwise C = 1. 
3 For non-addition/subtraction operation instructions that include shift operations, C is the last bit of the shifted value. 
4 For other non-addition/subtraction operation instructions, the value of C is usually unchanged.

V Overflow Set if overflow occurs. There are two ways to set the value of V: 
​​l For addition/subtraction instructions, when the operands and the result are signed numbers represented by binary complement, V = 1 indicates a sign overflow. 
2 For other non-addition/subtraction instructions, the value of V is usually unchanged. 
I IRQ Interrupt Disable 
F FIQ Fast Interrupt Disable 
T Working Status Bit, 1 for Thumb; 0 for ARM