ARM PLL-EEWORLD

Collect

Determine the PLL process:

1. Determine the CPU frequency Fcclk
2. Determine the crystal frequency Fosc, Fcclk must be an integer multiple of Fosc.
3. Calculate the M value M = Fcclk/Fosc, the value range of M is 1~32. The actual value written to the MSEL bit is an integer multiple of M-1.
4. Calculate the P value Select the P value to configure the PSEL bit. By setting the P value, make Fcco within the defined frequency limit range. P must be one of 1, 2, 4 or 8.

ARM PLL

PLL:

Fcco is the output frequency of the PLL current controlled oscillator
Fcclk = M×Fosc

Phase frequency detection: The phase difference of the two input clocks ==》 Current value

Current controlled oscillator: Current value ==》Frequency

When the two inputs are detected to be the same,

ARM PLL

the PLL locking process is stabilized:
The output frequency of the CCO is controlled by the "phase frequency detection" component. The process of outputting the required frequency is not achieved overnight, but a process of repeated tug-of-war.
ARM PLL

For example:

The system requires Fosc = 10MHz, Fcclk = 60MHz.
According to these requirements:

Determine Fcclk = 60MHz;
Select Fosc = 10MHz;
Calculate M = Fcclk/Fosc = 60MHz/10MHz = 6. M-1 = 5, so write PLLCFG[4:0] = 00101;
Calculate P = Fcco / (Fcclk * 2), where Fcco is 156 ~ 320 MHz. When Fcco = 156MHz, P = 156MHz / (2 * 60MHz) = 1.3 When Fcco = 320MHz, P = 2.67

P takes the integer 2, so write PLLCFG[6:5]=01

Keywords：ARM pll Reference address：ARM PLL

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