ARM Architecture Learning 3

　　The arrangement of each bit of the program status register is shown in the figure.

Figure 1.1 Program Status Register Format

　　1. Condition Code Flags

　　N, Z, C, and V are all conditional code flags. Their contents can be changed by the results of arithmetic or logical operations and can determine whether a certain instruction is executed.

　　In ARM state, most instructions are executed conditionally; in Thumb state, only branch instructions are executed conditionally. The specific meanings of each bit of the condition code flag are shown in Table 1.

　　(3) Operation mode bit M [4:0]: M0, M1, M2, M3, and M4 are mode bits that determine the operation mode of the processor. The specific meanings are shown in Table 2. Image loading...

Table 2 Specific meaning of operation mode bit M［4∶0］

　　As can be seen from Table 2, not all combinations of operating mode bits are valid, and other combinations will cause the processor to enter an unrecoverable state.

　　3. Reserved bits

　　The remaining bits in the PSR are reserved bits. When changing the conditional code flags or control bits in the PSR, the reserved bits should not be changed, and the reserved bits should not be used to store data in the program. The reserved bits will be used for ARM version extensions.

 

 

Complete list of assembly instructions:

1. Data transfer instructions────────────────────────────────────────They
transfer
data between memory and registers, and between registers and input/output ports.
1. General data transfer instructions.
MOV transfers words or bytes.
MOVSX sign-extends first, then transfers.
MOVZX zero-extends first, then transfers.
PUSH pushes words into the stack.
POP pops words out of the stack.
PUSHA pushes AX, CX, DX, BX, SP, BP, SI, DI into the stack in sequence.
POPA pops DI, SI, BP, SP, BX, DX, CX, AX out of the stack in sequence.
PUSHAD pushes EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI into the stack in sequence.
POPAD pops EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX out of the stack in sequence.
BSWAP swaps the order of bytes in a 32-bit register
XCHG swaps words or bytes.( At least one operand is a register, and segment registers cannot be used as operands)
CMPXCHG compares and exchanges operands. (The second operand must be the accumulator AL/AX/EAX)
XADD exchanges first and then accumulates. (The result is in the first operand)
XLAT byte table lookup conversion.
── BX points to the starting point of a 256-byte table, AL is the index value of the table (0-255, i.e.
0-FFH); AL is returned as the table lookup result. ( [BX+AL]->AL )
2. Input and output port transfer instructions.
IN I/O port input. (Syntax: IN accumulator, {port number│DX})
OUT I/O port output. (Syntax: OUT {port number│DX}, accumulator)
When the input and output port is specified by immediate mode, its range is 0-255; when specified by register DX,
its range is 0-65535.
3. Destination address transfer instruction.
LEA Load effective address.
Example: LEA DX, string; store the offset address in DX.
LDS Transfer target pointer and load the pointer content into DS.
Example: LDS SI, string; store the segment address: offset address in DS: SI.
LES Transfer target pointer and load the pointer content into ES.
Example: LES DI, string; store the segment address: offset address in ES: DI.
LFS Transfer target pointer and load the pointer content into FS.
Example: LFS DI, string; store the segment address: offset address in FS: DI.
LGS Transfer target pointer and load the pointer content into GS.
Example: LGS DI, string; store the segment address: offset address in GS: DI.
LSS Transfer target pointer and load the pointer content into SS.
Example: LSS DI, string; store the segment address: offset address in SS: DI.
4. Flag transfer instruction.
LAHF Flag register transfer, load the flag into AH.
SAHF Flag register transfer, load the content of AH into the flag register.
PUSHF Push flag on the stack.
POPF Pop flag from the stack.
PUSHD Push 32-bit flag on the stack.
POPD Pop 32-bit flag from the stack.

II. Arithmetic operation
instructions──────────────────────────────────────────
　　ADD Addition.
ADC Addition with carry.
INC Add 1.
AAA ASCII code adjustment for addition.
DAA Decimal adjustment for addition.
SUB Subtraction.
SBB Subtraction with borrow.
DEC Subtraction .
NEC Negate (subtract from 0).
CMP Compare. (Subtract two operands, only modify the flags, do not return the result).
AAS ASCII code adjustment for subtraction.
DAS Decimal adjustment for subtraction.
MUL Unsigned multiplication.
IMUL Integer multiplication.
For the above two operations, the results are returned to AH and AL (byte operation), or DX and AX (word operation),
AAM ASCII code adjustment for multiplication.
DIV Unsigned division.
IDIV Integer division.
For the above two operations, the results are returned:
the quotient is returned to AL, the remainder is returned to AH, (byte operation);
or the quotient is returned to AX, the remainder is returned to DX, (word operation).
AAD ASCII code adjustment for division
. CBW byte to word conversion. (Extend the sign of the byte in AL to AH)
CWD word to double word conversion. (Extend the sign of the word in AX to DX)
CWDE word to double word conversion. (Extend the sign of the word in AX to EAX)
CDQ double word extension. (Extend the sign of the word in EAX to EDX)

III. Logical operation
instructions───────────────────────────────────────
　　AND AND operation.
or OR operation.
XOR Exclusive OR operation.
NOT negation.
TEST test. (AND operation of two operands, only modify the flag bit, and do not return the result).
SHL logical left shift.
SAL arithmetic left shift. (=SHL)
SHR logical right shift.
SAR Arithmetic shift right. (=SHR)
ROL Rotate left.
ROR Rotate right.
RCL Rotate left through carry.
RCR Circular right shift through carry.
The above eight shift instructions can shift up to 255 times.
When shifting once, the operation code can be used directly. For example, SHL AX,1.
When shifting >1 times, the number of shifts is given by register CL.
For example, MOV CL,04
SHL AX,CL

IV. String instructions────────────────────────────────────────
DS
　:SI Source string segment register: source string displacement.
ES:DI Destination string segment register: destination string displacement.
CX Repeat counter.
AL/AX Scan value.
D flag 0 indicates that SI and DI should be automatically incremented in the repeat operation; 1 indicates that they should be automatically decremented.
The Z flag is used to control the end of the scan or comparison operation.
MOVS String transfer.
(MOVSB ​​transfers characters. MOVSW transfers words. MOVSD transfers double words.)
CMPS String comparison.
(CMPSB compares characters. CMPSW compares words.)
SCAS String scan.
Compare the contents of AL or AX with the target string, and the comparison result is reflected in the flag.
LODS Load string.
Load the elements (words or bytes) in the source string into AL or AX one by one.
(LODSB transfers characters. LODSW transfers words. LODSD transfers double words.)
STOS Save string.
It is the reverse process of LODS.
REP Repeat when CX/ECX<>0.
REPE/REPZ Repeat when ZF=1 or the comparison result is equal, and CX/ECX<>0.
REPNE/REPNZ Repeat when ZF=0 or the comparison result is not equal, and CX/ECX<>0.
REPC Repeat when CF=1 and CX/ECX<>0.
REPNC Repeat when CF=0 and CX/ECX<>0.

V. Program transfer
instructions───────────────────────────────────────
　1> Unconditional transfer instruction (long transfer)
JMP Unconditional transfer instruction
CALL Procedure call
RET/RETF procedure return.
2> Conditional transfer instructions (short transfer, within the range of -128 to +127)
(If and only if (SF XOR OF) = 1, OP1
JA/JNBE is not less than or equal to transfer.
JAE/JNB is greater than or equal to transfer.
JB/JNAE is less than transfer.
JBE/JNA is less than or equal to transfer.
The above four items test the results of unsigned integer operations (flags C and Z).
JG/JNLE is greater than transfer.
JGE/JNL is greater than or equal to transfer.
JL/JNGE is less than transfer.
JLE/JNG is less than or equal to transfer.
The above four items test the results of signed integer operations (flags S, O and Z).
JE/JZ is equal to transfer.
JNE/JNZ is not equal to transfer.
JC is transfer when there is a carry.
JNC is transfer when there is no carry.
JNO is transfer when there is no overflow.
JNP/JPO is transfer when the parity is odd.
JNS is the sign bit "0"
JO Transfer when overflow.
JP/JPE Transfer when parity is even.
JS Transfer when the sign bit is "1".
3> Loop control instructions (short transfer)
LOOP Loop when CX is not zero.
LOOPE/LOOPZ Loop when CX is not zero and flag Z=1.
LOOPNE/LOOPNZ Loop when CX is not zero and flag Z=0.
JCXZ Transfer when CX is zero.
JECXZ Transfer when ECX is zero.
4> Interrupt instruction
INT Interrupt instruction
INTO Overflow interrupt
IRET Interrupt return
5> Processor control instruction
HLT The processor pauses and continues until an interrupt or reset signal occurs.
WAIT When the chip lead TEST is high, the CPU enters the waiting state.
ESC Transfer to the external processor.
LOCK Block the bus.
NOP No operation.
STC Set the carry flag.
CLC Clear the carry flag.
CMC Invert the carry flag.
STD Set the direction flag.
CLD Clear the direction flag.
STI sets the interrupt enable bit.
CLI clears the interrupt enable bit.

VI. Pseudo-instructions────────────────────────────────────────
DW
defines a word (2 bytes).
PROC defines a procedure.
ENDP ends a procedure.
SEGMENT defines a segment.
ASSUME establishes segment register addressing.
ENDS ends a segment.
END ends a program.

VII. Processor control instructions: 
Flag processing instructions CLC (carry position 0 instruction)
CMC (carry bit negation instruction)
STC (carry position 1 instruction)
CLD (direction flag set 1 instruction)
STD (direction flag set 1 instruction)
CLI (interrupt flag set 0 instruction)
STI (interrupt flag set 1 instruction)
NOP (no operation)
HLT (stop)
WAIT (wait)
ESC (escape)
LOCK (lock)

 

Are assembly instructions conditional?

Operation Code	Condition code mnemonics	Logo	meaning
0000	EQ	Z=1	equal
0001	NE (Not Equal)	Z=0	not equal
0010	CS/HS (Carry Set/High or Same)	C=1	Unsigned greater than or equal to
0011	CC/LO (Carry Clear/LOwer)	C=0	Unsigned number is less than
0100	MI(MInus)	N=1	negative number
0101	PL(PLus)	N=0	Positive number or zero
0110	VS (oVerflow set)	V=1	overflow
0111	VC (oVerflow clear)	V=0	No overflow
1000	HI (HIgh)	C=1,Z=0	Unsigned number greater than
1001	LS (Lower or Same)	C=0,Z=1	Unsigned number less than or equal to
1010	GE (Greater or Equal)	N=V	Signed number greater than or equal to
1011	LT (Less Than)	N!=V	Signed number is less than
1100	GT (Greater Than)	Z=0,N=V	Signed number greater than
1101	LE (Less or Equal)	Z=1,N!=V	Signed number less than or equal to
1110	AL	any	Unconditional execution (default)
1111	NV	any	Never execute