ARM architecture analysis

Publisher:玄幻剑客Latest update time:2016-03-28 Source: eefocusKeywords:ARM Reading articles on mobile phones Scan QR code
Read articles on your mobile phone anytime, anywhere
Let's first talk about the history of ARM: On December 5, 1978, physicist Hermann Hauser and engineer Chris Curry founded CPU (Cambridge Processing Unit) in Cambridge, England, with the main business of supplying electronic equipment to the local market. In 1979, CPU was renamed Acorn Computer Company. (Excerpt from Baidu Encyclopedia)

 

In the mid-1980s, a small team at Acorn needed to select a suitable processor for their next-generation computer. According to the technical requirements they provided, they could not find a suitable processor on the market at that time, so Acorn decided to design a processor themselves (really bold). A small team completed the entire process from design to implementation in just 18 months. This is a computer with a RISC instruction set, called Acorn RISC Machine (ARM for short). Later, Acorn declined, and the processor design department was separated to form a new company.

 

ARM mainly designs ARM series AISC processor cores. It does not produce chips, but only provides IP cores. Let's first explain the architecture, core, processor and chip with an example: S3C2440, which is a SoC chip. Note that it is not a CPU. 2440 is somewhat similar to the 51 microcontroller we are familiar with. Both are embedded. The development of embedded has gone through three stages, namely SCM, MCU, and SoC. 51 belongs to SCM or MCU, while 2440 belongs to SoC. Let's first look at the internal structure of the 51 microcontroller.

Its internal structure can be simply divided into two parts: CPU and peripherals. Let's look at 2440:

 

The arm920t in the middle is its processor. In my opinion, processor and core are the same concept here, but one is a hard concept and the other is a soft concept. The 920t here is both a processor and a core. What Samsung does is other things besides this CPU.

 

 What about the architecture? Let's look at another picture.


The left side is the architecture, and the right side is the processor, also called the core. ARM's first and most successful CPU is ARM7TDMI, which is based on ARMv4. The ARM architecture includes the following RISC features:

Read/Store Architecture
Unaligned memory access is not supported (ARMv6 kernel now supports it)
Orthogonal instruction set (Orthogonal instruction set)
A large 16 × 32-bit register file
The fixed 32-bit operation code (opcode) length reduces the cost of encoding and reduces the burden of decoding and pipelining.
Most of them are executed in one CPU cycle.
Different versions of the architecture may have some adjustments.
 
Like Samsung, other major manufacturers that cooperate with ARM usually put their CPU and various peripheral IPs together, and then take the drawings to tape out the chips. The product is also a square with many pins underneath. This thing not only includes the CPU, but also other controllers. This thing is called SOC (system on chip). From the English point of view, the so-called quad-core SOC does not refer to the CPU alone, but the quad-core system.
So what major manufacturers do now is to buy ARM's authorization, get the source code of ARM processor, and then make some peripheral IPs (either buy or design them by themselves), form a SOC, and then go to tape-out. Different SOCs have different architectures (that is, how the CPU is connected to the IP, some are based on the bus, and some are based on DDR), so HiSilicon has its own SOC architecture. However, no matter which manufacturer, no matter how much they try, they have not touched the CPU, and the ARM core stays there, that is, the central processing unit.
At present, ARM's product ladder:


ARM naming convention:
The first number: series name: eg.ARM7, ARM9
The second number: Memory system
                    2: With MMU
                   4: With MPU
                   6: No MMU and MPU
The third number: Memory size
                    0: Standard Cache (4-128k)
                   2: Reduced Cache
                   6: Mutable Cache
The fourth character: T: indicates support for the Thumb instruction set
                   D: indicates support for on-chip debugging (Debug)
                   M: Indicates the built-in hardware multiplier (Multiplier)
                    I: Support on-chip breakpoints and debug points
                    E: indicates support for enhanced DSP function
                     J: indicates support for Jazelle technology, i.e. Java accelerator
                    S: indicates fully synthetic formula
References:
http://baike.baidu.com/view/4078025.htm?fr=aladdin
http://zh.wikipedia.org/wiki/ARM架構#cite_note-cortex-a50_announce-9
http://bbs.tianya.cn/post-worldlook-544367-1.shtml
Keywords:ARM Reference address:ARM architecture analysis

Previous article:Unaligned data access operations in ARM
Next article:Boot0 and boot1 of stm32

Recommended ReadingLatest update time:2024-11-17 01:48

2020 is not a good year for Arm
In the historic year of 2020, Arm is also undergoing its biggest test in history.   It can be said that Arm has had a bad year: the power-grabbing farce between Arm headquarters and Arm China has not yet ceased, and news about the price increase of Arm's IP licensing fees has also spread recently. What has attracted t
[Embedded]
2020 is not a good year for Arm
ARM startup code principle and analysis
Contents Content keywords: Image File RO Code Snippet ZI uninitialized data segment RW data segment Load Address Execu on A ddress Stack Pointer Stack space pointer Boot related hardware • Flash Rom (can be used as bootrom storage) Boot related hardware Boot related hardware Main functions of Boot •
[Microcontroller]
ARM startup code principle and analysis
Research and Simulation of ARM Parallel Bus Based on FPGA
    0 Introduction In the design of digital systems, the FPGA+ARM system architecture has been used more and more widely. FPGA mainly realizes high-speed data processing; ARM mainly realizes system process control, human-computer interaction, external communication and FPGA control functions. Serial bus interfaces
[Embedded]
Research and Simulation of ARM Parallel Bus Based on FPGA
ARM Basic Learning-Register
I learned assembly for a while in college, and now I find that I need to pick up these things and learn them again after I start working. In the next period of time, I will focus on the basic knowledge of ARM, then expand to ARMv8 to learn the 64-bit framework, and then learn MMU and its interrupt handling method; thi
[Microcontroller]
ARM Basic Learning-Register
Design of circuit module of fingerprint attendance system based on ARM7
  The attendance system has now become a must-have equipment for many companies, but the traditional attendance system is prone to replacing punching and swiping cards. The new fingerprint attendance machine completely avoids this situation. This article introduces a solution for designing a fingerprint attendance mac
[Microcontroller]
Design of circuit module of fingerprint attendance system based on ARM7
ARM4412 MMU memory management unit
Because when driving the bare board, it needs to be interrupted Exception MMU MMU is a memory management unit in the CP15 coprocessor, which is embedded in the ARM chip. Its function is to map virtual addresses to physical addresses. Before using the MMU register mechanism, you must first configure the register. The
[Microcontroller]
Part2_lesson1---Arm family review
Chips (such as 2440, 6410, 210, etc.) contain ARM cores. The instruction structure is related to the ARM core: ARM9 corresponds to the instruction architecture version ARMV4 ARM11 corresponds to the instruction architecture version ARMV6 Cortex A8 corresponds to the instruction architecture
[Microcontroller]
Part2_lesson1---Arm family review
Learn ARM development(18)
Last time, we have learned about the interrupt handling process of ARM and how to set the interrupt function. So, does it work like this? The answer is no. Because S3C44B0 has several registers that control whether the interrupt is turned on. These registers are as follows: 1. Program Status Register (CPSR).
[Microcontroller]
Latest Microcontroller Articles
  • Download from the Internet--ARM Getting Started Notes
    A brief introduction: From today on, the ARM notebook of the rookie is open, and it can be regarded as a place to store these notes. Why publish it? Maybe you are interested in it. In fact, the reason for these notes is ...
  • Learn ARM development(22)
    Turning off and on interrupts Interrupts are an efficient dialogue mechanism, but sometimes you don't want to interrupt the program while it is running. For example, when you are printing something, the program suddenly interrupts and another ...
  • Learn ARM development(21)
    First, declare the task pointer, because it will be used later. Task pointer volatile TASK_TCB* volatile g_pCurrentTask = NULL;volatile TASK_TCB* vol ...
  • Learn ARM development(20)
    With the previous Tick interrupt, the basic task switching conditions are ready. However, this "easterly" is also difficult to understand. Only through continuous practice can we understand it. ...
  • Learn ARM development(19)
    After many days of hard work, I finally got the interrupt working. But in order to allow RTOS to use timer interrupts, what kind of interrupts can be implemented in S3C44B0? There are two methods in S3C44B0. ...
  • Learn ARM development(14)
  • Learn ARM development(15)
  • Learn ARM development(16)
  • Learn ARM development(17)
Change More Related Popular Components

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号