ARM Microprocessor Programming Model-EEWORLD

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【Contents of this chapter】

Understand the structural characteristics of ARM

Understand the working mode of ARM programming

Learn about ARM's internal resources

Understand ARM's exception handling mechanism

【Chapter Structure】

【Working status of ARM microprocessor】

The ARM9 processor core uses the VT4 version of the ARM structure and has two operating states.

1) ARM state: 32 bits, executing word-mode ARM instructions;

2) Thumb state: 16 bits, executing half-word Thumb instructions;

(Both ARM and Thumb states are executing programs, but the length of the commands is different, similar to the nitrogen state and normal state in KartRider)

1) User and system modes;

(It feels similar to normal users and super users in Linux)

2) Abnormal mode

3) 7 register working modes supported by ARM9 processor

(ARM9 has 7 working modes, corresponding to 7 different register combinations (combinations of 37 internal registers))

[Organization of registers in ARM state]

1) General registers

(31 32-bit general purpose registers and 6 status registers (similar to a microcontroller))

R0-R12 are general registers for storing data or addresses and are not used for special purposes by the system or structure;

(R0-R7 are ungrouped registers: they can be used in any processor mode;

R8-R12 are grouped registers: depending on the current processor mode;)

(R8-R12: There are two grouped physical registers, providing a register dedicated to FIQ mode, which can speed up FIQ processing)

R13: Stack pointer (SP); there is no special R13 instruction in the ARM instruction set; there is an R13 instruction in Thumb

R14: Link register (LR), which has two special functions in structure (1. R14 of the mode itself is used to save the subroutine return address, 2. When an exception occurs, it is used to save the exception return address) [page]

2) Program Status Register (CPSR)

mode: indicates the working status of the processor

·T: 0, ARM state; 1, Thumb state;

Interrupt disable bits

I=1：Disables the IRQ

F=1: Disable the FIO

·condition code flags

N = Negative result from ALU (non-zero)

Z = Zero result from ALU

C = ALU operation Carried out

V = ALU operation Overflowed

v5, v6

Q: dsp extension unit

J: Java accelerator

(There are two ways for the processor to store data, big endian and little endian

Big endian: high byte in low order, low byte in high order

Little endian: high byte in high order, low byte in low order

*Old versions only support little-byte order, but now all versions are supported, and Linux network programming uses big-byte order)

[Exceptions supported by ARM]

(The processor will enter exception mode whenever the normal program flow is temporarily suspended. Before handling the exception, the ARM9 core saves the current processor state (CPSR->SPSR) so that when the processor ends it can resume execution of the original program (SPSR->CPSR))

Reset: reset interrupt;

Undefineed Instruction: Undefined instruction;

Software Interrupt: Software interrupt

Prefetch Abort: Prefetch instruction abort;

Date Abort: Data abort;

IRQ: external interrupt;

FIQ: Fast Interrupt Request;

Abnormal response

1) Entering exception:

*LR stores the address of the next instruction after the currently executed instruction: LR=PC-4

*CPSR->SPSR (retain status)

*CPSR->status corresponding to the exception type

* PC is fetched from the associated exception vector

* Jump, execute command

2) Return from an exception

*SPSR->CPSR

*The LR register value minus an offset is copied to the PC register and the interrupted user program is jumped

(Here, we can think about it in detail in combination with the 3-stage pipeline processing structure of ARM7, but why not save PC-8 in R14 in the first step?)

Keywords：ARM Reference address：ARM Microprocessor Programming Model

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