ARM-based hardware startup program design-initialization stack

ARM has 7 operating states, and the stack pointer register (SP) of each state is independent. Therefore, for each processor mode needed in the program, a stack address must be defined for SP. The process is: modify the status bit in the status register to switch the processor to the required mode, and then assign a value to SP. It should be noted that: do not switch to User mode to set the stack in this mode, because after entering User mode, you can no longer operate CPSR to return to other modes.

First define the value of the CPSR register M[4:0] corresponding to each mode. This value determines which mode to enter. Please refer to the relevant data manual.

Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F 
I_BIT EQU 0x80 ; when I bit is set (1), IRQ is disabled
F_BIT EQU 0x40 ; when F bit is set (1), FIQ is disabled

Here is the code snippet to initialize the stack:

InitStack    
        MOV R0, LR

; /* Set management mode stack*/
        MSR CPSR_c, #(Mode_SVC | I_BIT | F_BIT) ; 0xd3
        LDR SP, StackSvc
; /* Set interrupt mode stack*/
        MSR CPSR_c, #(Mode_IRQ | I_BIT | F_BIT) ; 0xd2
        LDR SP, StackIrq
; /* Set fast interrupt mode stack*/
        MSR CPSR_c, #(Mode_FIQ | I_BIT | F_BIT) ; 0xd1
        LDR SP, StackFiq
; /* Set abort mode stack*/
        MSR CPSR_c, #(Mode_ABT | I_BIT | F_BIT) ; 0xd7
        LDR SP, StackAbt
; /* Set undefined mode stack*/
        MSR CPSR_c, #(Mode_UND | I_BIT | F_BIT) ; 0xdb
        LDR SP, StackUnd
; /* Set system mode stack */
        MSR CPSR_c, #(Mode_SYS | I_BIT | F_BIT); 0xdf
        LDR SP, StackUsr

        MOV PC, R0

D CD AbtStackSpace + (
ABT_STACK_LEGTH - 1)* 4 StackUnd DCD UndtStackSpace + (UND_STACK_LEGTH - 1)* 4

; /* Allocate stack space*/
        AREA MyStacks, DATA, NOINIT, ALIGN=2
UsrStackSpace SPACE USR_STACK_LEGTH * 4 ;User (system) mode stack space
SvcStackSpace SPACE SVC_STACK_LEGTH * 4 ;Management mode stack space
IrqStackSpace SPACE IRQ_STACK_LEGTH * 4 ;Interrupt mode stack space
FiqStackSpace SPACE FIQ_STACK_LEGTH * 4 ;Fast interrupt mode stack space
AbtStackSpace SPACE ABT_STACK_LEGTH * 4 ;Abort mode stack space
UndtStackSpace SPACE UND_STACK_LEGTH * 4 ;Undefined mode stack

Let's take the management mode stack space as an example.

SVC_STACK_LEGTH is defined as 16, and the allocation results are: allocate 16 4-byte storage spaces, initialize the storage spaces to 0, and point SP to the bottom of the stack (high memory).

From the above memory content, we can see that the management mode stack allocates a total of 16*4 bytes from 0x00008080 to 0x00008044. The address 0x00008040 stores 0x00008080, which is the value of the pointer at the bottom of the stack.

That is, after the compilation, the 32-bit pseudo instruction StackSvc DCD SvcStackSpace + (SVC_STACK_LEGTH - 1)* 4 places the SvcStackSpace address value (0x00008080) at the address 0x00008040 (StackSvc). That is, 0x00008080 is assigned to SP.

Let's look at the contents at addresses 0x00008080~0x00008044. They are all andeq r0,r0,r0. Translated from the assembly instruction format, andeq r0,r0,r0 is exactly 0x000000000 after being translated into 16-disable code. Thus, the stack space is cleared to 0.