ARM hardware design: reset pin and sampling pin during reset

NRST input pin 

The NRST pin is used for master system reset. It resets all internal device registers, the program counter of the ARM core and the JTAG/ICE port when it is low. It samples the BMS and NTRI pins during system boot. NRST must be held until the power supplied to the microcontroller is stable and according to the start-up time of the external oscillator. The 

NRST pin must be kept at 0 level for at least 10 clock cycles before releasing the NRST pin so that the BMS and NTRI pins can be sampled correctly. 

Pins sampled during reset 

1. Boot mode select pin (BMS) 

The P25/BMS input pin is sampled on the rising edge of the NRST pin. This pin enables the ARM7TDMI core to start reading instructions from its internal flash memory, or one or more flash memories connected to the chip select 0 (NCS0) of the EBI. Once the BMS pin has been sampled during reset and the processor has been correctly initialized, the P25/BMS pin can be used as a general purpose I/O pin. 

Depending on the level of the BMS pin, the boot memory data bus width can be selected, 8 bits or 16 bits. Please refer to the data sheet for details. 

2. Tri-state input pins 

For debugging convenience, the AT91X40X series provides a tri-state mode. This enables the connection of an emulation probe from the target board to the application board. In tri-state mode, all output drive pins of the AT91X40X series microcontrollers are disabled. For the flash-based AT91FR40X series microcontrollers, the tri-state mode enables the programmer to treat the microcontroller like an ATMEL flash memory. 

When the user does not use the tri-state mode of the AT91 series, the NTRI pin must be pulled up through a 400KR resistor during reset. Note that the NTRI pin is multiplexed as the I/O line P21 and the TXD1 pin of USART1. If this pin is connected to a standard RS232 driver that contains an internal 400KR resistor, a pull-up resistor is not required. See RS232 Driver for details.