Improved System Design Based on ClearNAND Flash

　　Since its introduction, NAND flash memory has had increasing requirements for ECC (error correction code) error correction capabilities. Although this is not a new problem, the ECC error correction capabilities required to support the latest multi-level cell (MLC) architecture and three-bit-per-cell technology have become increasingly difficult for system personnel to cope with.

　　In the past, ECC has been used to improve the overall data reliability of NAND flash memory subsystems. However, as NAND cells continue to shrink, the number of electrons stored in each floating gate is decreasing. Therefore, to compensate for the higher bit error rate generated by smaller storage cells, the ECC error correction capability must be greatly improved to maintain the required system reliability.

　　As the system's requirements for ECC error correction continue to increase, the number of logic gates required to implement ECC logic is also increasing, and the system complexity is also increasing. For example, 24-bit ECC requires about 200,000 logic gates, while 40-bit ECC requires about 300,000 logic gates. It is estimated that advanced ECC algorithms in the future may require nearly 1 million logic gates (as shown in Figure 1).

Many high-performance flash memory systems must use multi-channel NAND flash memory to achieve ideal performance. In these systems, each channel has its own ECC logic. For example, a 10-channel solid-state drive (SSD) needs to implement 10 channels of ECC logic. If each of the 10 channels requires 60-bit ECC, then the ECC logic alone requires 3 million logic gates.

　　NAND Flash Interface Selection

　　1. Traditional NAND interface

　　The traditional NAND flash memory interface is an asynchronous communication interface. Although the speed of this interface has been increased to 50MHz in recent years, other characteristics have not changed much.

　　A few years ago, Micron and several other visionary companies jointly established a NAND flash memory organization to simplify the large number of timing and command standards in the industry. The Open NAND Flash Interface (ONFI) Alliance released its first version of the ONFI 1.0 specification. Compared with the original specification, the biggest feature of this interface specification is that the host processor can electronically identify the type of flash memory connected, as well as other important technical parameters such as timing mode, page size, block size, ECC requirements, etc. This feature is inherited by all ONFI standards and has always been an important part of all ONFI standards.

　　Another important achievement of the ONFI Alliance is the development of the synchronous NAND interface, which is also known as ONFI 2. Currently, the ONFI 2.2 specification supports up to 200 million transfers per second (200MT/s) through a DDR source synchronous interface. After power is applied, the interface can be used in asynchronous communication mode. However, for higher performance, when switching from asynchronous mode to synchronous communication mode, the host processor will ask the flash device in advance whether it supports the higher-speed synchronous communication interface.

　　2. Direct NAND solution

　　This solution manages NAND flash memory by connecting the NAND flash chip directly to the main processor or SSD controller. The ECC algorithm is handled by hardware, while software usually performs all block management and wear leveling functions. At first glance, this solution may not be ideal, but considering that today's embedded processors typically run at hundreds of megahertz, and many even exceed gigahertz, these high-performance processors can perform block management at a faster speed and use deterministic multi-threading technology to improve flash memory performance. In addition, because the main processor directly manages the flash device, the main processor software can make real-time decisions, which helps avoid the risk of unexpected power outages.

　　As shown in Figure 2, the ONFI 2.2 interface specification (200MT/s) can support up to 16 standard NAND flash memory chips. The typical solution usually uses two 8-chip NAND flash memory packages. The standard 8-chip 100-Ball BGA package contains two independent NAND buses (DQ［7:0］1 and DQ［7:0］2), each bus connecting 4 NAND flash memories. The flash memory controller controls each of the four stacked dies through two chip enable signals. The typical design is to connect the two data buses, namely the DQ buses, together to provide an 8-bit data bus for each package. The highest configuration consists of two 100-Ball BGA packages with 8 built-in dies. To select a specific NAND die, each standard 100-Ball BGA package needs to provide four chip enable (CE#) controls. Therefore, to support this configuration, the host processor or SSD controller needs to provide 8 chip enable signals.


3. ClearNAND Solution

　　Figure 3 shows two different system implementations: a traditional system where the host processor or SSD controller is directly connected to the NAND flash memory; and a system that uses ClearNAND flash memory chips. Both solutions use the same ONFI hardware interface and similar 100-Ball BGA packages, except that the latter integrates a thin controller with the NAND flash die in a multi-chip package (MCP). The ClearNAND controller is used to implement the ECC algorithm required for the NAND flash memory in the MCP package. Designers can easily upgrade from standard NAND flash to ClearNAND flash memory because the same ONFI asynchronous or synchronous interface is used.

　　Micron's ClearNAND flash memory is divided into two versions: standard and enhanced. Standard ClearNAND flash memory is mainly used in consumer electronic devices, which can implement the required ECC function and provide a traditional asynchronous ONFI bus for easy flash upgrade.

　　Enhanced ClearNAND flash memory can manage ECC algorithms and provide several key features that are valuable for enterprise applications. It also supports asynchronous and synchronous communication standards of the ONFI 2.2 interface, with available storage capacity up to 64GB.

　　By improving the ECC algorithm, both ClearNAND flash memory models can implement the ECC error correction function required by the next generation of NAND flash memory. This eliminates the need for designers to repeatedly redesign circuits to support manufacturers' latest NAND ECC requirements.


Enhanced ClearNAND flash memory

　　Figure 4 shows the architecture of the enhanced ClearNAND flash memory. It supports an ONFI 2.2 interface and command, address, and data buses with speeds up to 200 MT/s. The VDDI decoupling capacitors commonly found in e? MMC products and other flash memories with built-in controllers are used to decouple the internal voltage regulator. For backward compatibility with traditional NAND flash memories, the VDDI connection is placed on an unused pin. The ClearNAND controller supports two internal flash buses, one for even-numbered logical units (LUNs) and the other for odd-numbered logical units. These two independent flash buses have speeds of up to 200 MT/s. In addition, each bus has its own ECC engine that can manage reads or writes on both buses simultaneously. It is foreseeable that future controllers will also support the ONFI 3 interface specification for 400 MT/s.



The following will discuss four advanced features provided by enhanced ClearNAND: volume addressing, electronic data imaging, interrupt capabilities, and internal copyback. [page]

　　Volume Addressing

　　Volume addressing allows one chip select or chip enable signal (CE#) to address 16 ClearNAND volumes. Each ClearNAND controller supports stacking eight dies in one MCP package. The ClearNAND controller provides a buffer for host processor or SSD controller access operations.

As shown in Figure 5, the enhanced ClearNAND design increases storage capacity by eight times while maintaining or improving signal integrity and reducing the number of active chip enables required. This is because to the SSD controller, one ClearNAND controller represents only one load, but can support up to eight NAND dies in one MCP package.

　　The concept of volume addressing has two meanings. The first is determining the volume address for each ClearNAND package. The volume address is assigned only once at initialization and is saved until the power is cycled. The second meaning is the volume select instruction itself, which is followed by a single-byte (actually only 4 bits) volume address. Once the target address is selected, it will remain selected until another volume is selected. This can save a lot of enable pins. For example, a 32-channel SSD requires 8 enable pins to control two 8-die standard NAND packages. The above 32-channel SSD example requires a total of 256 enable pins, while the enhanced ClearNAND volume addressing feature only requires 32 enable pins to address the same amount of NAND flash. In addition, these same 32 enable pins can address eight times the existing capacity.

　　Electronic Data Image

　　Enhanced ClearNAND supports electronic data mapping, which allows the data bus signal sequence to be electronically remapped to one of two configurations. This feature is useful for high-density designs that have ClearNAND flash mounted on both the front and back sides of the PCB. The ClearNAND package can electronically detect whether the flash is mounted on the front or back side of the PCB using a special initialization or reset sequence. For example, a common practice is to send a reset or FFh command to the flash after power-up. To complete the electronic DQ mapping, the host processor must follow the FFh command with a traditional READ STATUS (70h) command. The flash mounted on the front side of the PCB detects the FFh-70h command sequence; the flash mounted on the back side of the PCB detects the FFh-0Eh command sequence and confirms to the host processor that it is a backside flash package, and then reroutes the data bus directly behind the front side flash, which not only improves PCB routing but also improves signal integrity.

　　Ready/Busy# is redefined as interrupt

　　Enhanced ClearNAND Flash memory redefines the existing ready/busy# pin as an interrupt pin. As shown in Figure 6, the interrupt# signal is still an open-drain signal that provides a real-time interrupt signal when the ClearNAND volume or die is ready. Designers can use this interrupt signal to provide real-time status of the flash memory to the host processor or SSD controller. In large configurations that support multiple ClearNAND packages on a single bus, the interrupt# signal lines can be connected together. When an interrupt signal is detected, the host processor or SSD controller only needs to query each ClearNAND package or volume to know which volume sent the new status information. This interrupt feature saves the number of signals on the host processor or SSD controller while improving the responsiveness of the SSD controller to status updates.


Internal Write Back

　　Internal write-back, also known as internal data move, is one of the most compelling features of enhanced ClearNAND flash. Wear leveling or defragmentation of flash refers to the process of collating data fragments within different NAND flash pages and blocks and merging them into new blocks or sequences of blocks, similar to the defragmentation tools of old hard drives. For such operations, write-back can provide a huge advantage for SSD systems.

　　Referring back to Figure 2, when using standard NAND flash, moving a data fragment from one block to another typically requires the following operations:

　　The SSD controller issues a READ instruction and source address to access the data source page; the SSD controller reads data from the NAND flash memory, performs calculations and necessary ECC error correction operations, and then implements data or metadata update operations; the SSD controller calculates and adds new ECC information, and then issues a new PROGRAM instruction, destination address, and data sequence, which will save the data to a new NAND flash memory block.

　　During this continuous operation, the bus is occupied while the data is moved from the source address to the destination address, and this operation takes a long time. Assuming an 8K memory page, the ONFI 2.2 synchronous bus operating at 200MT/s takes about 41μs to move the data. Because the data must be moved out and then moved into the flash memory, it takes twice as long, or 82μs, but this time does not include the time spent by ECC. During the execution of this sequence, the ONFI flash bus is always occupied and cannot process any other operations.

　　Unlike ordinary flash memory, enhanced ClearNAND flash memory supports internal ECC. If the source address and destination address of the data are both within the ClearNAND package, the internal ECC can perform write-back operations within the package. The SSD controller is still responsible for issuing instructions and addresses, as well as modified data or metadata. The ClearNAND controller performs data migration operations without occupying the external ONFI data bus. If the SSD controller can integrate wear leveling and fragmentation cleaning functions into a ClearNAND package, it will have a stronger advantage in performance.

　　Figure 7 shows an example of using Enhanced ClearNAND Flash on two ONFI channels labeled Channel 0 and Channel 1. On both SSD channels, we see four internal data migration operations occurring simultaneously without occupying the external ONFI bus for data movement. This feature allows the SSD controller and ONFI bus to migrate data between ClearNAND packages when necessary. Depending on the architecture used by the user, some operations may need to be performed between ClearNAND packages or even between ONFI buses. Utilizing internal data migration operations can greatly improve the performance of defragmentation and wear leveling operations.


　　Conclusion

　　Micron's enhanced ClearNAND flash memory provides system designers with higher performance and more features while alleviating the increasingly stringent requirements for ECC error correction capabilities of NAND flash memory. Enhanced ClearNAND flash memory supports a similar solder ball arrangement as standard 100-Ball BGA NAND flash memory, and users can design products that support both packages. For example, this product will enable SSD host controllers to have sufficient ECC error correction capabilities to directly support SLC NAND flash memory. Choosing enhanced ClearNAND flash memory can also meet the requirements of multi-level cells where ECC faces greater challenges.

　　The enhanced ClearNAND flash volume addressing feature enables larger capacity addressing with fewer pins, saving hundreds of pins in SSD solutions. The electronic data image function simplifies PCB design and routing while improving the signal integrity of the ONFI bus. The smart interrupt function provides real-time status update information to the SSD controller and minimizes polling of the firmware. The two-way internal NAND flash bus improves write-back capabilities, thereby improving flash performance.