Principle of single chip microcomputer reset circuit

Function of reset circuit

During the power-on or reset process, control the reset state of the CPU: keep the CPU in the reset state during this period, instead of working as soon as the power is turned on or the reset is completed, to prevent the CPU from issuing erroneous instructions and performing erroneous operations, and also to improve electromagnetic compatibility performance.

No matter what type of MCU the user uses, the design of the MCU reset circuit is always involved. The quality of the MCU reset circuit design directly affects the reliability of the entire system. Many users have encountered "freeze" and "program error" on site after designing the MCU system and successfully debugging it in the laboratory. This is mainly caused by the unreliable design of the MCU reset circuit.

Basic reset method

The microcontroller needs to be reset when it starts up, so that the CPU and various system components are in a certain initial state and start working from the initial state. The reset signal of the 89 series microcontroller is input from the RST pin to the Schmitt trigger in the chip. When the system is in normal working state and the oscillator is stable, if there is a high level on the RST pin and it lasts for more than 2 machine cycles (24 oscillation cycles), the CPU can respond and reset the system. The reset methods of the microcontroller system are: manual button reset and power-on reset

1. Manual button reset

Manual button reset requires a high level to be added to the reset input terminal RST (Figure 1). The general method is to connect a button between the RST terminal and the positive power supply Vcc. When the button is pressed manually, the +5V level of Vcc will be directly added to the RST terminal. The circuit of manual button reset is shown as follows. Since the button will remain connected for tens of milliseconds no matter how fast the human action is, it can fully meet the reset time requirement.

2. Power-on reset

The power-on reset circuit of AT89C51 is shown in Figure 2. Just connect a capacitor to the Vcc terminal on the RST reset input pin and a resistor to the ground. For CMOS microcontrollers, since there is a pull-down resistor inside the RST terminal, the external resistor can be removed and the external capacitor can be reduced to 1µF. The working process of power-on reset is that when power is applied, the reset circuit adds a short high-level signal to the RST terminal through the capacitor. This high-level signal gradually falls back as Vcc charges the capacitor, that is, the duration of the high level at the RST terminal depends on the charging time of the capacitor. In order to ensure that the system can be reset reliably, the high-level signal at the RST terminal must be maintained for a long enough time. When powered on, the rise time of Vcc is about 10ms, and the start-up time of the oscillator depends on the oscillation frequency. For example, if the crystal frequency is 10MHz, the start-up time is 1ms; if the crystal frequency is 1MHz, the start-up time is 10ms. In the reset circuit of Figure 2, when Vcc loses power, the voltage at the RST terminal will inevitably drop rapidly to below 0V. However, due to the limiting effect of the internal circuit, this negative voltage will not damage the device. In addition, during the reset period, the port pins are in a random state. After the reset, the system sets the ports to all "1" states. If the system does not get an effective reset when powered on, the program counter PC will not get a suitable initial value, so the CPU may start executing the program from an undefined position.

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3. Integral power-on reset

The commonly used power-on or switch reset circuit is shown in Figure 3. After power-on, due to the charging of capacitor C3 and the action of the inverting gate, RST remains at a high level for a period of time. When the microcontroller is already running, pressing and releasing the reset key K can also make RST a high level for a period of time, thereby realizing the power-on or switch reset operation.

Based on actual operating experience, the reference values ​​of capacitance and resistance of this reset circuit are given below.

In Figure 3: C: = 1uF, Rl = lk, R2 = 10k

Dedicated chip reset circuit:

The function of the power-on reset circuit in the control system is to start the microcontroller to work. However, when the power is turned on and the voltage is abnormal or disturbed during normal operation, the power supply will have some unstable factors, which may have a serious impact on the stability of the microcontroller. Therefore, a reset signal is output to the chip after a delay when the power is turned on. Another function of the reset circuit is to * the power supply voltage during normal operation. If the power supply is abnormal, a forced reset will be performed. The reset output pin needs to output a low level for three (12/fc s) or more instruction cycles, and the reset program starts to initialize the initial state inside the chip. Waiting for receiving input signals (such as signals from remote controls, etc.).

Analysis of the Principle of Power-On Reset Circuit

The 5V power supply is input through the 2nd pin of MC34064, and the 1st pin can output a rising edge to trigger the reset pin of the chip. The electrolytic capacitor C13 is used to adjust the reset delay time. When the power is turned off, the residual charge on the electrolytic capacitor C13 forms a loop through D13 and the internal circuit of MC34064, and the charge is released. It is ready for the next reset.

4. Key components of the power-on reset circuit

The key components are: MC34064.

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Transistor undervoltage reset circuit

欠压复位电路工作原理(图6)w 接通电源，+5V电压从“0V”开始上升，在升至3.6V之前，稳压二极管DH03都处于截止状态，QH01(PNP管)也处于截止状态，无复位电压输出。w 当+5V电源电压高于3.6V以后，稳压二极管DH03反向击穿，将其两端电压“箝位”于3.6V。当+5V电源电压高于4.3V以后，QH01开始导通，复位电压开始形成，当+5V电源电压接近+5V时，QH01已经饱和导通，复位电压达到稳定状态。

Watchdog reset circuit

The watchdog reset circuit mainly uses the CPU to reset the counter regularly when it is working normally, so that the value of the counter does not exceed a certain value; when the CPU cannot work normally, since the counter cannot be reset, its count will exceed a certain value, thereby generating a reset pulse, so that the CPU returns to normal working state. The typical application of the Watchdog reset circuit is shown in Figure 7. The reliability of this reset circuit mainly depends on the software design, that is, where the program that sends pulses to the reset circuit regularly is placed. Generally, this program is placed in the timer interrupt service subroutine. However, sometimes this design still causes the program to run away or work abnormally. The main reason is that when the program "runs away", after the timer is initialized and the interrupt is turned on, this "runaway" situation may not be corrected by the Watchdog reset circuit. Because the timer interrupt is really generated, even if the program is abnormal, the Watchdog can be reset normally. For this reason, a design method of adding a preset to the timer is proposed. That is, an address is pushed into the stack during initialization, and a statement of disabling interrupts and an infinite loop is executed at this address. All addresses not occupied by program code are replaced with the subroutine return instruction RET as much as possible. In this way, when the program runs away, the possibility of entering a trap will be greatly increased. Once the trap is entered, the timer stops working and turns off the interrupt, so that the watchdog reset circuit will generate a reset pulse to reset the CPU. Of course, this technology has certain difficulties in using it in real-time control or processing software.

Figure 7 Watchdog reset circuit

Comparator type reset circuit

The basic principle of the comparator reset circuit is shown in Figure 8. During power-on reset, since an RC low-pass network is formed, the voltage at the positive input of the comparator is delayed by a certain time compared to the negative input voltage. The time constant of the negative network of the comparator is much smaller than the time constant of the positive RC network. Therefore, when the positive voltage has not exceeded the negative voltage, the comparator outputs a low level and generates a high level after the inverter. The width of the reset pulse mainly depends on the speed of normal voltage rise. Since the time constant of the negative voltage discharge circuit is large, it is not sensitive to the fluctuation of the power supply voltage. However, the following two unfavorable phenomena are prone to occur: (1) When the interval of the secondary switch of the power supply is too short, the reset is unreliable; (2) When there is a surge in the power supply voltage, the reset pulse may not be generated after the surge disappears. For this reason, the comparator reset circuit will be improved, as shown in Figure 9. This improved circuit can eliminate the first phenomenon and reduce the occurrence of the second phenomenon. In order to completely eliminate these two phenomena, the digital logic method can be used in conjunction with the comparator to design the comparator reset circuit shown in Figure 9. This circuit can be used as a reset circuit for both power-on reset and watchdog reset circuit with a little improvement, which greatly improves the reliability of reset.

Figure 9 Improved comparator reset circuit