Analysis and Design of ARM Processor Startup Code

ARM architecture

At present, the ARM series of general-purpose 32-bit RISC microprocessors include ARM7, ARM9, ARM9E, ARM10 and other products. These processors can work in 7 modes. All modes except User mode are called privileged modes, and the other 5 modes except User and System are called exception modes. Most applications run in User mode. When the processor is in User mode, the executed program cannot access some protected system resources to facilitate the use of system resources by the operating system, and the mode cannot be changed, otherwise an exception will occur. For System mode, no exception will cause entry into this mode, and the registers it uses are basically the same as those in User mode. It is mainly used for operating system tasks that have access to system resources but avoid using additional registers. In privileged mode, they can fully access system resources and can change modes freely. When handling specific exceptions, the system enters the corresponding exception mode. These 5 exception modes have their own additional registers to avoid conflicts with programs in user mode when exceptions occur.

In any processor mode, the same register is used to identify the current processor working mode. This register is called CPSR (Current Program Status Register). Its 0~4 bits are used to indicate the CPU mode. In each processor exception mode, there is a corresponding SPSR (Cache Program Status Register) to save the value of the CPSR before entering the exception mode. The function of SPSR is that when the CPU exits from the exception mode, a simple assembly instruction can restore the CPSR before entering the exception mode. The value is saved in the SPSR of the current exception mode.

Design of startup code

The startup code is similar to the BIOS in a computer. It takes over the CPU from the moment the system is powered on. It is responsible for initializing the CPU stack space in various modes, setting the CPU memory map, initializing various control registers of the system, initializing the CPU external memory, setting the base address of each peripheral device, creating the correct interrupt vector table, creating the ZI (zero creation) area for C code execution, and then entering the C code. In the C code, the clock and RS232 port are initialized, and then the system interrupt enable bit is turned on. Finally, the application code is executed, responding to various interrupt signals during execution and calling pre-set interrupt service routines to handle these interrupts. The flowchart of the entire process is shown in Figure 1.

Figure 1 Startup code flow chart

Stack initialization

The initialization of the stack is to allocate stack space for the 7 processor modes of the processor. The following is an example of the stack setting in FIQ mode:

ORR r1, r0, #LOCKOUT | FIQ_MODE; put the mode in r1, LOCKOUT is used to mask the interrupt bit;

MSR cpsr, r1; change the CPU's CPSR register to enter the specified FIQ mode;

MSR spsr, r2; save the previous mode;

LDR sp, =FIQ_STACK; assign the stack start value in FIQ mode to the current SP, FIQ_STACK is the start address of the stack space allocated to FIQ mode (for example, 1K bytes). Set up the stack in other modes in this way. [page]

DRAM initialization is determined by the system configuration information, because the system may not necessarily use DRAM, but SDRAM initialization must be done. The main processing content is the setting of ROM and RAM base addresses, the width of the data bus, the refresh time of SDRAM, etc. These can be referred to the user manual of the S3C4510B chip. The setting of special registers is mainly for I/O ports, for example, setting several I/O bits to be used as system status indicator LEDs. The setting of registers is mainly based on the hardware configuration. It is worth noting that since this startup code is burned into ROM, and the interrupt vector must be located at zero address, the ROM base address should be set to zero address before the storage unit is remapped.

Copying (image) is mainly to increase the running speed. The compiled image file code is copied from ROM to RAM, and the program is executed in RAM. Of course, the startup code does not have a very strict requirement for the running speed, so this copying action can be omitted, so that the code is stored in ROM, the code is also executed in ROM, and the data required for operation is in RAM.

Memory initialization is to open up memory areas for the operation of C code. After the code is compiled, it will be divided into three areas: read-only area, readable and writable area,

Zero initialization area. The initialization process of the memory is as follows: when the end address of the read-only area is equal to the base address of the readable and writable area, clear all bytes in the zero initialization area; when the end address of the read-only area is not equal to the base address of the readable and writable area, if the base address of the readable and writable area is less than the zero initialization base address, copy the data from the end address of the read-only area to the base address of the readable and writable area until the zero initialization base address is reached, and then clear all bytes in the zero initialization area, otherwise, only clear all bytes in the zero initialization area.

The interrupt vector table is used to handle exceptions. When an exception occurs, the return address of the current program and the value of the CPSR register must be saved first, and then enter the corresponding exception vector address. Generally speaking, the exception vector address is a jump instruction, which allows the program to enter the corresponding exception handling process. Since the interrupt vector table must be located at the zero address of the system, when the startup code is burned into the EEPROM and run, the address of the ROM needs to be defined to the zero address, so the entry point of the program is as follows:

System remapping When you copy the ROM Image to RAM to increase the running speed, the interrupt vector table is not at the zero address, so you need to remap the storage unit and reset the RAM address to zero address. Mapping is to copy the startup code from ROM (EEPROM or Flash) to SDRAM for execution, and remap the memory after the copy is completed, mapping SDRAM to the original ROM address (0x0000), so that the code in SDRAM can be used to write Flash, so that the program code can be updated. However, it should be noted that if the program is mapped, it will bring difficulties to online debugging, making online debugging impossible to perform in RAM (if the code written to EEPROM is mapped, the program will inevitably be mapped when the debugger is started, so that the program cannot be located at the original location in the debugger, causing debugging to fail). A compromise method is not to map, that is, downloading cannot be used in the debugged code, so that it can be debugged like ordinary code.

Conclusion

After completing these initializations, switch the CPU to user mode and assign the stack pointer SP to the user stack area, then enter the C code area to run. Continue to initialize the clock and RS232 port in the C code, then turn on the system interrupt enable bit and enter the application code to execute. This program is loaded into S3C4510B and debugged. The CPU can start normally and respond to interrupt requests in a timely manner. The main code of the upper-level application can be loaded into the Flash. After transplanting the real-time operating system RTXC, the scheduling control of multi-tasks is normal.

References:
1. Steve Furber, 'ARMSoC Architecture'. Beijing University of Aeronautics and Astronautics Press, 2002.
2. Ma Zhongmei, 'ARM Embedded Processor Architecture and Application Basics', Beijing University of Aeronautics and Astronautics Press, 2003.
3. Li Juguang, 'Detailed Explanation of ARM Application System Development - System Design Based on S3C4510B', Tsinghua University Press, 2003.

4. RISC datasheet http://www.dzsc.com/datasheet/RISC_1189725.html.
5. RS232 datasheet http://www.dzsc.com/datasheet/RS232_585128.html.
6. ROM datasheet http://www. dzsc.com/datasheet/ROM_1188413.html.
7. S3C4510B datasheet http://www.dzsc.com/datasheet/S3C4510B_589499.html.