Multi-channel USB2.0 data acquisition system based on AT91SAM7X

At present, most of the USB devices used in industry and medicine are connected to the microprocessor using a dedicated USB chip , especially the USB data acquisition system. According to different requirements, a certain number of A/D converters are usually required to be expanded, and the interface is very complicated. Sometimes it is even necessary to expand the FIFO to coordinate different clocks. Such a design not only greatly increases the cost, but also seriously threatens the stability of the system. This article uses the ARM-based flash microcontroller AT91SAM7X chip developed by Atmel. The chip integrates 8-way 10-bit ADC and USB2.0 device interface. The single chip can complete the design task, avoiding the complex interface circuit design, which not only effectively solves the above problems, but also greatly improves the stability of the system.

1 Introduction to AT91SAM7X data acquisition master chip

AT91SAM7X is a microcontroller based on the 32-bit ARM7TDMI core. The AT91SAM7X series of microcontrollers has an embedded 10/100M Ethernet MAC, CAN, and full-speed (12 Mbps) USB 2.0. Designed for a wide range of networked real-time embedded systems, the AT91SAM7X256 also has a 10-bit analog/digital converter (ADC), two serial peripheral interfaces (SPI), a synchronous serial interface (SSC), a two-wire interface (TWI), three universal asynchronous receivers and transmitters (UARTs), an 8-level priority interrupt controller, and numerous supervisory functions. This new 50MIPS MCU has 64 KB of static memory and 256 KB of 25 ns flash memory, which supports the deterministic processing capabilities required for real-time control systems.

2 Data Acquisition System Hardware Design

2.1 Data Acquisition System Hardware Design Structure Diagram

The multi-channel USB2.0 data acquisition system based on AT91SAM7X designed in this paper mainly consists of 6 parts, as shown in Figure 1, namely the input signal interface module, multi-channel signal amplification module, signal conditioning module, data acquisition processing module, USB2.0 interface module and host computer module. Among them, the input signal interface module, multi-channel signal amplification module and signal conditioning module mainly complete the isolation access and conversion of the external standard -5~+5 V signal. Because the conversion voltage range allowed by the ADC of AT91SAM7X is 0~3 V, the signal conversion of the above three processes is necessary. The main conversion method used in this system is differential amplification of the signal. The main parts of the data acquisition processing module and the USB2.0 interface module are completed by the built-in ADC module and USB2.0 module of AT91SAM7X respectively. Since most of the work is completed inside the same chip, the data acquisition and transmission process can be completed by simple register settings and data exchange, which optimizes the design of the system to a great extent.

2.2 Introduction to ADC module of AT91SAM7X

The ADC on the AT91SAM7X is based on the continuous register (SAR) model. An 8-to-1 analog multiplexer is used to implement 8-channel analog/digital conversion. The ADC input range is OV to ADVREF. The ADC supports 8-bit and 10-bit resolutions. The ADC can be started by software trigger, external ADTRG trigger pin, or internal trigger timer. The ADC accuracy can be improved by configuring the ADC clock, start time, and sample hold time. The ADC is not managed by the power manager and has an interrupt source. If the ADC interrupt signal is used, the interrupt controller (AIC) needs to be configured.

2.3 Introduction to USB2.0 module of AT91SAM7X

AT91SAM7X has a built-in USB device controller. The USB device port complies with the USB2.0 full-speed device specification and has a communication rate of 12 Mbps. Each endpoint can be configured as one of several USB transfer types. The USB device automatically detects suspend and resume and stops the processor through interrupts . At the same time, in order to cooperate with the use of USB devices and maximize their performance, a 328-byte dual-port RAM is integrated on the chip. One DPR segment of this dual-port RAM is read/written by the processor, and the other DPR segment is read/written by the USB2.0 peripheral, which effectively guarantees the maximum bandwidth of data transmission.

3 AT91SAM7X Configuration and Module Programming

3.1 ADC module configuration and module programming

The functional block diagram of the ADC module is shown in Figure 2. The ADC module is a 10-bit analog/digital converter based on a successive approximation register (SAR) and integrates an 8-to-1 analog multiplexer to achieve analog/digital conversion of 8 analog signals . The conversion is from OV to ADVREF. At the same time, the ADC supports 8-bit or 10-bit resolution mode, and the conversion result enters a general register (i.e., channel-specific register) available to all channels. It can be configured as software trigger, external trigger ADTRG pin rising edge, or internal trigger timing counter output. The ADC also integrates a sleep mode and a conversion sequence generator, and is connected to the PDC channel. These features can reduce power consumption and reduce processor interference. Finally, the user can configure the ADC time, such as the start time and the sampling and holding time.

In the system design, multi-point A/D conversion is performed, and ADVREF is connected to a 3.0V reference voltage. For convenience, a single-point conversion is used as an example to illustrate the configuration and module programming of the ADC module. Of course, before A/D conversion, the system clock and overall configuration are required. Here we only introduce the configuration and module programming related to the ADC module. First, clear all registers related to analog/digital conversion to ensure that all registers have a certain value. The specific configuration process and IAR program code are as follows:

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3.2 USB2.0 module configuration and firmware programming

The USB2.0 interface module is shown in Figure 3. The module requires two clocks, namely the USB2.0 device port clock and the main clock. The module accesses the USB2.0 device port through the APB bus interface. The dual-port RAM that stores data is read/written by reading/writing the 8-bit value of the APB register. The external resume signal is optional, allowing the USB2.0 device port peripheral to be woken up in system mode, and then the host will notify the device requesting recovery. This feature must be handled by the host when the USB2.0 interface is enumerated. In order to retain the I/O line that checks VBUS, the PIO controller must be programmed first and the I/O must be configured as input PIO mode. There is an interrupt line in the USB2.0 device that is connected to the advanced interrupt controller AIC. Therefore, when handling USB2.0 device interrupts, the advanced interrupt controller AIC must be programmed before configuring the USB2.0 device port.

This system uses the USB2.0 interface to communicate with the host computer. For the sake of convenience, here we take the example of transmitting numbers 0 to 9 to the host computer through the USB2.0 interface and looping 10 times to explain the configuration and programming of the USB2.0 module. After the system is initialized, this firmware program sends numbers 0 to 9 through the USB2.0 interface and ends after 10 loops. The specific configuration process and IAR program code are as follows:

Note: During the debugging process of USB2.0 communication interface 121, the USB2.0 firmware program must be downloaded to the F1ash of AT91SAM7X. This process can be completed through ARM address remapping, and then the USB2.0 interface is powered on again, because the host computer detects the device only when the device is inserted and prompts to add the corresponding driver. If the developer only loads the program into RAM during debugging, the data will not be saved when the power is off, and the firmware program will not exist when the device is inserted next time. No matter what driver is added to the host computer, the host computer will not receive the data, which will cause the failure of the entire debugging process.

3.3 USB2.0 Windows Application Design

The host computer part realizes USB communication with the embedded hardware part through Visual C++6.0 program. During the test, the USB2.0 firmware program is first downloaded to AT91SAM7X, the USB data cable is plugged in, and the corresponding driver is added according to the prompts, and then the designed Visual C++6.0 program is directly run. The test results are shown in Figure 4.

During the operation of the host computer program, the connection status of the device is first checked. After confirming the successful connection, it starts to receive the data sent by the USB2.0 device. Here are the numbers 0 to 9 that are cycled 10 times. As shown in Figure 4, the data has been successfully transmitted to the host computer.

Conclusion

This paper designs a multi-channel USB2.0 data acquisition system based on AT91SAMTX, and uses AT91SAM7X chip as the core to realize the conditioning, conversion, acquisition and transmission of data signals to the host computer. Since AT91SAM7X has built-in ADC module and USB2.0 device interface, the system design is very convenient; at the same time, since there is no need to use a large number of external expansion chips, the hardware cost is greatly reduced, the product size is smaller, and the stability is greatly improved compared with the external expansion chip method.