Design and implementation of LCD display system based on PXA270

introduction

Xscale processor is an ARM processor based on ARMv5TE architecture launched by Intel. PXA270 is a full-performance, cost-effective, low-power Xscale processor launched by Intel in the fourth quarter of 2003, with a maximum main frequency of 624MHz.

The PXA270's Quick Capture, Wireless MMX and Wireless Speed ​​Step technologies greatly enhance multimedia processing capabilities while minimizing power consumption on mobile devices while ensuring CPU performance.

Embedded Linux refers to a special Linux operating system that is tailored to the standard Linux system and can be embedded in a memory chip or microcontroller with a capacity of only a few KB or MB. It is suitable for specific embedded applications. About half of the successfully developed embedded systems use Linux.

1 LCD liquid crystal display principle

Embedded systems generally use liquid crystal display (LCD). This system uses LG Philiph's TFT 6.4-inch true color display LP064V02.

The principle of liquid crystal display is that liquid crystal will show different light characteristics under the action of different voltages. TFT is the abbreviation of Thin Film Transistor. FB (Frame Buffer) is the frame buffer.

A complete picture displayed on the display is a frame. The entire display area has a corresponding storage space in the system. By changing the content of the storage space, the content of the display can be changed. This storage space is called Frame Buffer. Each point on the display must correspond to a certain position in the Frame Buffer. The color displayed by the computer is represented by RGB values. Therefore, if you want to display a certain color at a certain point on the screen, you must give the corresponding RGB value. Frame Buffer is an external memory area used to store the encoding and pixel value of the entire display. Each byte of the frame buffer corresponds to a pixel in the LCD. For example, the LP064V02 display has 640×480=307200 pixels.

2 LCD controller built into PXA270

2.1 LCD Controller Introduction

The data transmission between the Frame Buffer and the LCD display is very frequent, and it is obviously not suitable to be driven directly by the CPU through the program. Therefore, in order to reduce the burden on the CPU, a middleware is required between the Frame Buffer and the display. The middleware is responsible for extracting data from the Frame Buffer, processing it, and transmitting it to the display.

The LCD controller consists of the following parts: LCD DMAC (the DMAC mentioned in this article refers to the DMAC integrated inside the LCDC), input/output FIFO, internal palette, TMED dither (frame rate control), and register group.

The internal operation mode of LCDC will vary depending on the type of LCD connected. This system uses the active 16-bit pixel mode. In this active color mode, the internal working mode of LCDC is relatively simple. The data in the Frame Buffer is 16-bit pixel data. At this time, LCDC does not need to load data into the internal palette, and the data does not need to be processed by the frame rate control unit. It is directly sent to the data pin of the LCD controller. After being transmitted to the input FIFO through DMAC, the data is immediately transmitted to the output FIFO.

2.2 LCD module hardware connection

The hardware connection between PXA270 and LCD module is shown in Figure 1. The description of each signal pin is as follows:

Figure 1 LCD interface block diagram

• L_DD[15:0]: Data line. The 16-bit data line can display red, green, and blue pixels. Using 5 bits of red, 6 bits of green, and 5 bits of blue can achieve different color displays.
• L_PCLK: pixel clock. Used to input color data into the shift register in the LCD display. In passive mode, the pixel clock only jumps when the data on the data line is valid; in active mode, the pixel clock jumps continuously.
• L_LCLK: Line scan clock. It is used to end the line display of the LCD display and send the line data of the shift register to the display, and increase the line pointer by 1. In active mode, it is the horizontal synchronization signal.
• L_FCLK: Frame scan clock. Used for the start of a new frame pixel of the LCD display. When the display is reset, the row pointer points to the top of the display. In active mode, it is a vertical synchronization signal.
• L_BIAS: AC bias. In active mode, it is the data enable signal.

3 Design and implementation of LCD driver

The PXA270 embedded system drives the LCD display in two aspects: one is the initialization of the LCD and related components, including the creation of the frame buffer and the setting of the DMA channel; the other is the reading and writing of the frame buffer. The transmission of the frame buffer content to the LCD display is completed by hardware and is transparent to the driver. [page]

3.1 Frame Buffer Initialization

The main data structures are as follows:

struct pxafb_info: mainly used to build the frame buffer device driver framework, and is also the driver layer interface defined by Linux for frame buffer devices. It not only contains the underlying functions, but also records all the information of the frame buffer device. Each frame buffer device must correspond to an fb_info structure. The member variable modename is the device name, fontname is the display font, and fbops is a pointer to the underlying operation function.

struct pxafb_fix_screeninfo: records display controller parameters that cannot be modified by the user. It includes the physical address and length of the screen buffer.

struct pxafb_var_screeninfo: records the display controller parameters that can be modified by the user. It includes the resolution of the display screen, the number of bits per pixel, and some timing variables. The variable xres defines the number of pixels occupied by a row of the screen, yres defines the number of pixels occupied by a column of the screen, and bits_per_pixel defines how many bits are used to represent each pixel.

The initialization function of the frame buffer is in the /drivers/video/pxafb.c file and has the following structure:

int __init pxafb_init(void)

{

struct pxafb_info *fbi;

int ret;

…………

fbi = pxafb_init_fbinfo(); //Initialize some important data structures

…………

/* Initialize video memory */

ret = pxafb_map_video_memory(fbi); //Create an image buffer in memory

…………

pxafb_set_var(&fbi->fb.var, -1, &fbi->fb);

…………

ret = register_framebuffer(&fbi->fb); //Register to hook the frame buffer to the high-level console device driver

…………

/ * Ok, now enable the LCD controller  */

set_ctrlr_state(fbi, C_ENABLE);

…………

return right;

}

First, pxafb_init_fbinfo() is called to initialize several data structures and set relevant basic parameters, such as the font used, display specifications, etc., and to prepare for the device driver framework for building the frame buffer. Then, the frame buffer is created in memory through the pxafb_map_video_memory() function, which actually creates another mapping for a memory interval. The memory interval allocated for the frame buffer here should be non-cached and non-write buffered, so that it can be reflected on the display immediately after writing without refreshing the cache first.

The pxafb_set_var() function provides an interface for the console device driver to drive the frame buffer. It also determines some parameters related to the frame buffer and records them in a fb_var_screeinfo data structure. After determining these parameters, if the target frame buffer belongs to the currently selected console device, the pxa_activate_var() function combines these parameters in different categories to generate images of the relevant registers of the PXA270, and finally sets them to the various LCD control registers of the PXA270.

Six registers are used here:

• DBAR1: Base address register of DMA channel 1, used for palette;
• DBAR2: base address register of DMA channel 2, used for drawing;
• LCCR0: black and white/color mode selection, single screen/dual screen display mode, passive/active display mode selection;
• LCCR1: controls the horizontal scanning, including the number of pixels per line, the width of the horizontal sync pulse, and the number of pixels left blank at the beginning and end of the horizontal scanning line.
• LCCR2: controls the vertical scanning, including the number of lines in each picture, the width of the vertical synchronization pulse, the number of lines left blank at the top and bottom of the picture, etc.
• LCCR3: controls the frequency of the pixel clock and the polarity of various synchronization pulses.

[page]

These macro operations are all in the /drivers/video/pxafb.h file.

#if defined(CONFIG_FB_LB064v02)

#define LCD_PIXCLOCK        250000//54000//150000

#define LCD_BPP             16

#define LCD_XRES            640

#define LCD_YRES            480

#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 46

#define LCD_VERTICAL_SYNC_PULSE_WIDTH   1

#define LCD_ BEGIN_OF_LINE_WAIT_COUNT    96

#define LCD_BEGIN_FRAME_WAIT_COUNT    35

#define LCD_END_OF_LINE_WAIT_COUNT     4

#define LCD_END_OF_FRAME_WAIT_COUNT    0

#define LCD_SYNC    (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)

#define LCD_LCCR0   (LCCR0_OUC | LCCR0_CMDIM | LCCR0_RDSTM | LCCR0_OUM | LCCR0_BM | LCCR0_QDM | LCCR0_PAS |LCCR0_EFM | LCCR0_IUM | LCCR0_SFM | LCCR0_LDM )

#define LCD_LCCR3                   (LCCR3_PCP | LCCR3_HSP | LCCR3_VSP)

#endif

Finally, register_framebuffer() is used to register various things and connect the frame buffer to the upper layer of the console device driver. The parameter fbi is a pointer to the fb_info data structure, which connects the frame buffer to the file system.

3.2 Frame Buffer Operation

To operate the frame buffer, the application must first open the device file representing the frame buffer. The file_operations data structure of the frame buffer is fb_fops.

static struct file_operations fb_fops = {

owner:                 THIS_MODULE,

read: fb_read, // read operation

write: fb_write, // write operation

ioctl: fb_ioctl, // control operation

mmap: fb_mmap, // mapping operation

open: fb_open, // open operation

release: fb_release, // close operation

#ifdef HAVE_ARCH_FB_UNMAPPED_AREA

get_unmapped_area: get_fb_unmapped_area,

#endif

};

The access of the application layer to the frame buffer device is similar to the access to the file. In the application, the operation of the frame buffer device (dev/fb) only needs to call the operation function of the file layer. First, open the /dev/fb device file; then use the ioctl operation to obtain the screen resolution and bpp value, so as to calculate the size of the screen buffer, and map the screen buffer to the user space; finally, the screen buffer can be directly displayed. The file opening operation of the frame buffer is completed by fb_open(), etc.

Once the driver is written, the developer can compile it into dynamic loading mode or statically compile it into the kernel.

4 Conclusion

With the advent of the post-PC era, embedded systems have been used more and more widely. Today's embedded systems generally need to provide a graphical human-computer interface. The system designed in this paper runs well and has stable performance. It has achieved relatively satisfactory economic benefits in actual products.

References:

1. Chen Wenzhi, "Principles and Practices of Embedded System Development", Tsinghua University Press, 2005.8

2. Xu Qingfeng, Design and Implementation of Color LCD Driver under Embedded Linux, Electronic Products World 2003.Z2

3. Wang Tongyang, Xiong Wei, Research and Design of Graphical User Interface in Embedded Linux, Microcomputer Information, 2006, No. 3-2

4. Internal information of Shenzhen Yidao Electronic Technology Co., Ltd.