Digital power amplifier design using Atmega8

1. Introduction

Digital power amplifiers are increasingly widely used in real life due to their high efficiency and easy connection with digital audio sources. It mainly consists of two parts. Figure 1 is the basic block diagram of a digital power amplifier. There are two types of PWM conversion. One is analog PWM, which is to compare the input analog signal or digital signal with the triangle wave after D/A. This conversion must have a triangle wave with a frequency of hundreds of kHz, good linearity, and full amplitude, and a high-speed analog comparator, otherwise it will affect the waveform of the PWM waveform after demodulation, which will increase the cost and design complexity (the use of integrated Class D power amplifiers or Class D control chips is another matter). The second is digital PWM, which is to compare the input digital signal or analog signal with the counter after A/D, that is, to use the counting method instead of the triangle wave, thereby avoiding the distortion caused by the nonlinearity of the triangle wave. Compared with the traditional analog method, the digital method has the advantages of simple design, higher efficiency, and stronger anti-interference. The timer 1 in the Atmega8 microcontroller can work in PWM mode. It can complete PWM modulation by simply moving the value in its AD to the PWM output compare register, which is quite simple to implement.

In order to increase the output power, most Class D amplifiers are driven by BTL. Whether it is analog or digital PWM, there are two options for the selection of BTL two-way output signals, namely in-phase drive and anti-phase drive. In the former, the superposition effect of the two signals is almost zero when the signal is zero, while in the latter, the voltage superimposed on the filter will become larger when the signal is zero. Of course, the voltage drop on the load can be reduced by modifying the filter parameters, but this will increase the system power consumption and is not convenient for overall implementation. Therefore, this paper selects digital PWM and adopts in-phase drive to realize the digital power amplifier function, thereby further reducing static power consumption and improving efficiency.

2 Hardware Design

The hardware circuit of this design is divided into three parts, including preamplification, A/D and PWM conversion, power amplification and filtering, etc. The principle of the hardware circuit is shown in Figure 2. The PWM frequency of this system must be modulated to at least 5 times the highest frequency of the signal (20 kHz) to ensure a good restoration of the audio signal. If the operating frequency is 16 MHz, the maximum count value of the PWM (hereinafter referred to as TOP) will be: fCLK-I/O/fpwm=16MHz/100kHz=160. In addition, the sampling value of the A/D (maximum 255) must also be divided by a certain value to be used as the value of the PWM output comparison register (hereinafter referred to as OCR1A/OCR1B), which will obviously reduce the equivalent accuracy of the AD. To ensure the original accuracy of the AD and the PWM frequency, the crystal oscillator should be increased. After testing: mega8 can still work normally at 32MHz. At this time, the AD sampling value can be directly used as the OCR1A/OCR1B value. At this time, the PWM frequency is 32MHz/255=125.5kHz.

2.1 Preamplification

The preamplifier is mainly composed of AD's low-power, low-noise, single-power, rail-to-rail input and output amplifier AD8605 and a digital potentiometer. The quiescent current of AD8605 is only 0.9mA (5V), the power supply range is 2.7V~5.5V, and the bandwidth is 10MHz. The digital potentiometer X9C102 has 100 steps, the size is 1kΩ, and the minimum can reach 40Ω. It and AD8605 can form a common-mode amplifier. R2 in Figure 2 is selected as 1kΩ, and the amplification factor can be adjusted between 2 and 250.

2.2 A/D and PWM part

The A/D and PWM in this design are all completed by mega8. In the AVR family, Atmega8 is a very special single-chip microcomputer. It integrates a large-capacity memory and rich hardware interface circuits. It has all the performance and characteristics of the AVR high-end single-chip microcomputer MEGA series, but because it uses a small pin package (DIP 28), its price is comparable to that of low-end single-chip microcomputers, so it has a very high cost performance. In addition, it has ISP function and is extremely convenient to download. Atmega8 single-chip microcomputer has complete functions and rich interfaces. It has 6 channels of A/D, including 4 10-bit A/D and 2 8-bit A/D. The 3 PWM channels in the chip can realize any pulse width modulation output less than 16 bits, as well as adjustable phase and frequency. In addition, each I/O pin in Atmega8 adopts push-pull drive, so it can not only provide large current drive, but also absorb 20mA current. Atmega8's PWM has three working modes: fast PWM mode, phase adjustable PWM mode and phase frequency adjustable PWM mode. The latter two use a two-way counter, so their PWM frequency is only half of the fast mode. This article uses the first working mode. This mode is completed using timer/counter 1, and the counter is a one-way upward addition of 1, from 0x00000 to TOP, cleared when the next count pulse arrives, and then counts by 1 from 0x00000. When setting the positive comparison match output, when the count value is the same as the value of OCRR1A/OCRR1B, the output comparison match bit (hereinafter referred to as OCRR1A/OCRR1B) is set. When the counter value returns from TOP to 0x000, OCRR1A/OCRR1B is cleared. When setting the reverse comparison output, its output is exactly the opposite of the same direction comparison. From the perspective of the two-way PWM generation process, the changes in the two ways are simultaneous, thus avoiding the extra loss caused by the different delays of the two ways. [page] 2.3 Power Amplification Part

The power amplifier uses two IRF7389s, each with a pair of VMOS tubes built in. The on-resistance of the N-channel and P-channel are 46 and 98 mΩ respectively. When VGS = 4.5V, the maximum output power is 30W. In addition, the IRF7389 also has a built-in high-speed recovery diode to reduce harmonic distortion. C17 and C16 in Figure 2 are acceleration capacitors that can be used to improve the excitation waveform so that the VMOS tube can quickly switch from cut-off to on-state, or from on-state to cut-off, so as to reduce the dead time and improve the output waveform. R7 and R8 in Figure 2 mainly play a protective role.

3 Software Design and System Experiment

The system software consists of AD interrupt service program, timer interrupt service program, PWM program and key interrupt service program.

After the system is powered on, the AD interrupt program, clock interrupt program, and PWM program are initialized first, and then the AGC control of the volume is performed at the initial stage of program operation. Considering the logarithmic relationship of the human ear to the intensity of the received sound, the gain of the amplifier is designed to increase logarithmically from 2 times to 20 times, without manually adjusting the amplification factor, so that the output can be guaranteed to be within a certain range, so that the amplifier works in the linear region. The specific process is shown in Figure 3. During the playback process, the volume can be adjusted by calling the interrupt subroutine by pressing a key.

When the conversion accuracy of Atmega8 AD conversion is less than 10 bits, the sampling clock of ADC can be higher than 200 kHz, so a higher sampling rate can be obtained. In addition, setting the ADHSM bit in the SFIOR register can increase the clock frequency of ADC. This system uses the internal reference power supply and continuous conversion mode of ADC, and selects ADC4 channels (accuracy is 8 bits). The experimentally measured conversion speed can reach 40 kHz.

The initialization of PWM A and B channels adopts the same working mode. When there is zero input, A and B are output in phase. When a positive signal is input, the pulse width of channel A increases. At this time, since the comparison value of channel B is complementary to that of channel A, the pulse width of channel B decreases. When there is a negative signal input, the pulse width of channel A decreases and the pulse width of channel B increases.

Through testing, the maximum output of this system under 5V power supply and 8Ω load is 8.4V (i.e. 4.2×2) without losing the peak-to-peak value of true sine wave, the output power is 1.1W, the power supply current is 278mA at 16MHz, and the efficiency is 80%. At 32MHz, the equivalent accuracy of AD will be improved, the sound quality will be better, but the static power consumption current of the system will increase. However, since the loss is basically fixed, it is more suitable to use Atmega8 to design digital power amplifier in higher power occasions. In addition, increasing the voltage between the source of IRF7389 can increase the output PWM level, thereby increasing the output power and further improving the efficiency.

4 Conclusion

The design of the power amplifier using the Atmega8 single-chip microcomputer is very simple, flexible, and scalable. It can also meet different needs by adjusting the program. The frequency response of the power amplifier can be changed by modifying the digital filter program. If a memory is added, recording, repeating, setting the playback time and displaying the volume can be realized. These functions cannot be achieved by integrating only the Class D power amplifier.