Design of USB mobile storage interface based on CH375

O Introduction

With the rapid development of USB technology, USB mobile storage devices are increasingly used. Currently, some instruments and equipment with data acquisition and analysis functions provide USB interfaces. Among the many USB mobile storage device interface chips, CH375 is a domestically produced chip with a very high cost performance. Here we introduce some practical experience of using this chip in battery activation detection equipment for readers' reference.

1 CH375 functions and features

1.1 Chip Overview

CH375 is a USB bus universal interface circuit that supports HOST mode and SLAVE mode. On the local side, CH375 has an 8-bit data bus and read, write, chip select control lines and interrupt output, which can be easily connected to the system bus of microcontrollers/DSP/MCU/MPU and other controllers. In USB host mode, a serial communication mode is provided, which is connected to microcontrollers/DSP/MCU/MPU and other controllers through serial input, serial output and interrupt output. External microcontrollers/DSP/MCU/MPU can communicate with USB devices through CH375 according to the corresponding USB protocol, which simplifies the design and development of USB work for designers. The application block diagram is shown in Figure 1.

1.2 Internal structure

CH375 integrates PLL frequency multiplier, master-slave USB interface SIE, data buffer, passive parallel interface, asynchronous serial interface, command interpreter, protocol processor for control transmission, general firmware program, etc.

The CH375 chip has 7 physical endpoints inside. Endpoint O is the default endpoint, supporting upload and download, and the upload and download buffers are 8 B each; Endpoint 1 includes upload endpoints and download endpoints, and the upload and download buffers are 8 B each. The endpoint number of the upload endpoint is 81H, and the endpoint number of the download endpoint is 01H; Endpoint 2 includes upload endpoints and download endpoints, and the upload and download buffers are 64 B each. The endpoint number of the upload endpoint is 82H, and the endpoint number of the download endpoint is 02H. The host endpoint includes output endpoints and input endpoints, and the output and input buffers are 64 B each. The host endpoint and endpoint 2 share the same set of buffers. The output buffer of the host endpoint is the upload buffer of endpoint 2, and the input buffer of the host endpoint is the download buffer of endpoint 2. Among them, endpoints 0, endpoint 1, and endpoint 2 of CH375 are only used in USB device mode. In USB host mode, only the host endpoint is needed. The internal interrupt logic diagram of CH375A is shown in Figure 2.

1.3 Chip Characteristics

(1) Low-speed and full-speed USB-HOST host interface, support LISB 2.0, peripheral components only need 1 crystal and 2 capacitors; (2) Low-speed and full-speed USB device interface, support dynamic switching between host and device mode;
(3) Host endpoint input and output buffers are 64 B each, support commonly used 12 Mb/s full-speed USB devices and 1.5 Mb/s low-speed devices;
(4) Support control transmission, bulk transmission, and interrupt transmission of USB devices;
(5) Automatically detect the connection and disconnection of USB devices, and provide event notifications of device connection and disconnection;
(6) Built-in control transmission protocol processor to simplify commonly used control transmission;
(7) Built-in firmware handles the dedicated communication protocol of mass storage devices;
(8) Parallel interface includes 8-bit data bus, 4-wire control: read enable, write enable, chip select input and interrupt output;
(9) Serial interface includes serial input, serial output and interrupt output, support dynamic adjustment of communication baud rate;
(10) Support 5 V power supply voltage and 3.3 V power supply voltage, support low power mode. [page]

2 Hardware Circuit Design

2.1 Block diagram of battery activation equipment

Battery activation equipment is an intelligent device that integrates multiple functions of battery data collection, analysis and activation processing. During the activation process, the terminal voltage of each group of 24 batteries needs to be sampled and stored in real time for analysis and processing by the upper-level analysis software. Traditional equipment and upper-level software generally transmit data through the RS 232 serial communication port. In actual application, the computer must be carried to the site, and the computer must be equipped with serial port hardware, which is extremely inconvenient to use.

Here, an intelligent battery activation device based on the CH375A USB interface chip is proposed, so that the battery activation device has a universal USB interface, providing a simple and convenient data communication method for smart devices and computers, and has the advantages of simple operation and convenient use. The battery activation device system is shown in Figure 3, and its working principle is described as follows.

The battery activation equipment system uses ATMEGA64 single-chip microcomputer + U disk master chip CH375A to realize the reading and writing of U disk, and store each working status and parameter value of the battery activation equipment in a separate file according to a fixed format, which can provide the upper-level analysis software with necessary information such as base station information, battery pack information, battery pack charge and discharge status, battery charge and discharge current, set charge and discharge time, actual charge and discharge time, battery pack open circuit voltage, battery pack voltage, single battery voltage, battery pack current, battery pack temperature, alarm, etc. Here we focus on the application of CH375 chip, and do not introduce other functional circuits in the system.

2.2 CH375 and ATMEGA64 MCU interface principle

Figure 4 shows the hardware circuit of the ATMEGA64 microcontroller implementing the USB interface through CH375.

In this design, CH375 works in USB-HOST host parallel interface mode, that is, the TXD pin of CH375 chip is directly grounded, so that CH375 is connected to the system bus of 8-bit single-chip microcomputer through passive parallel interface circuit. The 8-bit bidirectional data bus D0~D7 of CH7375 is directly connected to the PA data port of single-chip microcomputer, and RD and WR are connected to the read strobe output pin and write strobe output pin of single-chip microcomputer respectively. The chip select signal CS is connected to the P14 pin of system decoding circuit 74HCl38, and CH375 is selected when the pin is low. INT is connected to the interrupt input PE7 pin of single-chip microcomputer, and the interrupt request is valid at low level. Single-chip microcomputer obtains interrupt request through interrupt mode. The address input line AO ​​is connected to the PD4 pin of single-chip microcomputer. When the AO pin is high level, the command port is selected, and commands can be written; when the AO pin is low level, the data port is selected, and data can be read and written.

3 Software Design

CH375 can support various common USB full-speed devices. For USB devices that comply with the Mass-Storage communication protocol, the built-in firmware can directly communicate through the Mass-Storage communication protocol. For USB devices that do not meet the above requirements, an external microcontroller is required to handle the relevant communication protocol by controlling the transmission and the ISSUE_TOKEN command or the ISSUE_TKN_X command.

3.1 Local MCU Software

The microcontroller reads and writes the CH375 chip through the 8-bit parallel port. All operations consist of a command code, some input data, and some output data. Some commands do not require input data, and some commands do not have output data. The command operation steps are as follows:

(1) Write the command code to the command port when A0=1;
(2) If the command has input data, write the input data in sequence when A0=0, 1 byte at a time;
(3) If the command has output data, read the output data in sequence when A0=0, 1 byte at a time;
(4) After the command is completed, you can pause or go to (1) to continue executing the next command.

The CH375 chip is specially used to process USB communication. When it detects a change in the status of the USB bus or the completion of a command, the CH375 notifies the microcontroller in an interrupt mode for processing.

3.2 UBS interface software program flow

HC375 is not only a universal USB-HOST hardware interface chip, but also has built-in related fixed programs, which can easily realize the management of the USB storage device file system. In this application, C language programming is used to store the battery processing data in the form of a file each time. The program supports file opening, creating, deleting, reading and writing functions. The communication process between the device and the USB storage device mainly includes the initialization of the CH375 chip, status query and parallel data collection. The communication part program flow is shown in Figure 5.

4 Conclusion

Here, the CH375 chip is successfully used in the USB interface circuit of the battery activation device, and a satisfactory operation effect is achieved. The design can well realize the data transfer of the detection equipment, which provides great convenience for the users of the battery activation device. The results show that the use of the CH375 chip in the design of the USB data mobile storage interface circuit has the advantages of simple software and hardware interface design, high cost performance, and easy operation.