LTC2207 data acquisition application under ARM and FPGA control

Introduction
Data acquisition technology is a popular and practical electronic technology. It is widely used in signal detection, signal processing, instrumentation and other fields. In recent years, with the continuous development of digital technology, data acquisition technology has also shown a development trend of higher speed, more channels and larger data volume.
The core device of the data acquisition system in this design is Linear Technology's A/D conversion chip LTC2207. This paper studies the acquisition application of DC data and sinusoidal signals under the control of ARM core S3C2440 chip and FPGA, and conducts relevant simulation verification.

1 Introduction to LTC2207 chip
1.1 Functional characteristics of LTC2207
LTC2207 is a 16-bit A/D converter with a sampling rate of 105Msps. LTC2207 is designed for digital processing of high-frequency and wide dynamic range signals with an input frequency of 700 MHz. It can optimize the input range of the ADC using the PGA front end (input range of 1.5Vp-p or 2.25Vp-p).
LTC2207 is very suitable for demanding communication applications. Its AC performance includes 78.2 dB noise floor and 100 dB spurious-free dynamic range (SFDR); SFDR>83 dB at 250 MHz (when the input range is 1.5Vp-p); ultra-low jitter of 80fSRMS enables undersampling of high input frequencies and excellent noise performance; maximum DC specifications include ±4LSB INL, ±1LSB DNL (no missing codes) over the entire temperature range.
The LTC2207 has a single 3.3 V power supply, and a single power supply allows the CMOS output swing to be 0.5 to 3.6 V. It also has a 700MHz full-power bandwidth S/H (sample and hold), an optional internal jitter and data output (Randomizer) random function generator, and a power consumption of 900 mW. The LTC2207 can use a sine wave clock, PECL, LVDS, TTL or CMOS input to drive the ENC+ and ENC- inputs differentially or single-ended. The optional clock duty cycle stabilizer achieves high performance at full speed and multiple clock duty cycles.
The pin description of LTC2207 is briefly explained in the editor's note.
1.2 Timing description of LTC2207
The timing diagram of LTC2207 is shown in Figure 1. LTC2207 is a CMOS multi-step converter with a front-end PGA. The analog input is a differential signal to improve common-mode noise rejection and maximize the use of the input range. In addition, the differential input signal can reduce the harmonics of the sample-and-hold circuit. The encoding input also has a stronger anti-interference ability than the common-mode rejection input.

The acquisition of LTC2207 depends on the state of ENC+/ENC- input pins. As shown in Figure 1, LTC2207 samples the analog input signal at the rising edge of ENC+ pin (falling edge of ENC- pin). It has 5 pipeline analog-to-digital conversion stages. After 7 cycles, an analog sample input will be converted to a digital value. The digital output overflow/underflow is indicated by the logic high level on the OF pin.
This A/D converter has a delayed encoding input as a digital output, providing two signals CLKOUT+ and CLKOUT-; the sinusoidal clock encoding signal CLKOUT+/CLKOUT- is required to synchronously convert the data to the digital system. The data is latched at the rising edge of CLKOUT+ or the falling edge of CLKOUT-, and updated at the falling edge of CLKOUT+ and the rising edge of CLKOUT-.

2 Hardware Circuit Design
The signal acquisition part mainly completes the conditioning of analog signals and the acquisition of A/D conversion chips. The input signal of the A/D conversion chip is differential, while the signal to be collected is single-ended, which requires converting the single-ended signal into a differential signal. After the input signal is buffered by MAX4201, it is converted into a differential signal by the differential driver AD8131 to drive the A/D conversion chip LTC2207.
The LVDS repeater MAX9150 is used to convert the clock signal given by the FPGA as the collection control signal ENC of LTC2207. The conversion circuit of MAX9150 is shown in Figure 2.

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The conditioning chip of the analog differential signal input front end of LTC2207 uses low noise, low power consumption, ultra-high speed open-loop buffer MAX4201 and high speed differential driver AD8131. The front-end conditioning circuit for collecting input signals is shown in Figure 3. In the figure, MAX4201 uses ±5 V power supply, and the capacitor connected in parallel to the ground filters the power supply to provide interference-free power supply for the buffer. The buffered signal is output from pin 5 of MAX 4201, and its output impedance is 50 Ω, and then the single-ended to differential conversion is completed by AD8131.

The acquisition control circuit of LTC2207 is shown in Figure 4. Among them, AIN+ and AIN- are differential analog input signals; ENC+ and ENC- are clock control signals of the acquisition chip; D0~D15 are 16-bit data output signals; CLKOUT+ and CLKOUT- are clock output signals.

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3 ARM and FPGA programming control
Using the hardware description language Verilog HDL, the program for enabling the relevant pins of LTC2207 and how FPGA reads the collected data is as follows:

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4 Simulation Verification The
simulation verification is performed using the debugging tool SignalTapII logic analyzer in QuartusII software. When the acquisition input is 0.453 V DC, the data collected by FPGA is simulated as shown in Figure 5.
It can be observed that the data 3337h, 3333h, 332Bh, 3337h, etc. do not change much, and only the lower 5 bits change. According to the A/D acquisition principle, input voltage/reference voltage = sampling value/216. The given reference voltage is 2.25 V. If the sampling value is 3334h in the above data (any one is selected from the relatively stable data), it is converted into decimal 13108 and substituted into the above formula: 13108×2.25/65536=0.45. The input voltage calculated by the data read by FPGA is 0.45 V, while the actual input voltage measured at this time is 0.453 V. The error is very small, about 0.6%, which is basically caused by noise, and the data collected is relatively accurate.
When the acquisition input is 1.125 V DC, the data collected by FPGA is simulated as shown in Figure 6. Similarly, if 7FE0h is taken, the calculated error is about 0.8‰.
When the acquisition input is 1.16 V DC, the data collected by FPGA is simulated as shown in Figure 7.

It can be seen from the figure that the data under this input has reached the full value (input exceeds 1.125 V), and OF is high, indicating that the data has overflowed.
When the acquisition input is a 200 kHz sine signal given by the signal generator, the data simulation collected by FPGA is shown in Figure 8.
From the formula of the number of sampling points in one cycle N=Tsig/Tsam=fsam/fsig, it is known that the number of sampling points under this input frequency is 40 MHz/200 kHz=200. If you look at OF17h at the coordinate -250, find out whether the number after one cycle is the same as the initial value. The data simulation when the FPGA coordinate is 150 is shown in Figure 9. It is located at OF07h at the coordinate 150, which is very different from OF17h. Taking the corresponding multiple groups of observations proves that the data acquisition of analog signals is also relatively correct.

Conclusion
For the A/D conversion chip LTC2207, the sampling design using FPGA and ARM as controllers is described in detail. The A/D is configured directly using FPGA, avoiding the traditional configuration method of using DSP, single-chip microcomputer, etc., so the design is flexible, simple and versatile. Through simulation verification of the collected data, it is found that the 16-bit A/D chip LTC2207 has been well collected and applied under the control of ARM and FPGA.