Achieving near-determinism in microcontrollers with cache and on-chip flash

In order to control the actuator, the real-time control system receives input signals from sensors and outputs command signals to the actuator after control operations. These outputs must be triggered within a specified time after receiving the input - that is, the system must have real-time performance; at the same time, for the same input under the same control state, the output should always be the same - that is, the system must be deterministic.

Developments in many areas of the electronics industry are making these basic real-time control systems increasingly complex. On the one hand, control algorithms are becoming more sophisticated, reaching the level of artificial intelligence in decision-making. On the other hand, these control systems are increasingly connected to the Internet, both locally via Ethernet or wireless local area networks (LANs) and over long distances via the Internet. In addition, user interfaces are becoming increasingly complex and security requirements are becoming increasingly stringent, making data encryption and verification of the legitimacy of external control sources essential system features.

These trends require processors with more powerful processing power and higher communication bandwidth. The processor must be able to respond to real-time input signals in a certain way, and there must be enough memory to handle various network communications as a low-priority task. However, in many cases, system upgrades for improved performance require retaining the original device drivers, network protocol stacks, and some basic operations that serve as the basis for control algorithms. This is especially true when using industry-standard processor architectures, such as 32-bit ARM RISC. Figure 1 shows an example of an MCU upgrade that follows these two principles, that is, upgrading from the ARM7-based AT91SAM7X series to the ARM9-based AT91SAM9XE series. Both series of devices have on-chip flash memory for storing program code and reference data.

One important difference between the two families is that the ARM9 processor has instruction and data caches, while the ARM7 processor does not. Caches help mitigate the performance degradation caused by the difference in capabilities between the processor and memory (the former can run code at about 200MIPS, while the latter can only transfer data at about 25MHz). It is well known that it is impossible to achieve complete determinism in a system using caches. However, many architectural features of the ARM926EJ-S processor and AT91SAM9XE microcontroller family allow application developers to achieve near-deterministic real-time performance.

High-speed cache + wide data bus on-chip flash memory

Many architectural features can maximize the internal data transfer bandwidth. As shown in Figure 2, taking the AT91SAM9XE series as an example, in addition to having separate 16Kb instruction and data caches that can operate at processor speed, a 7-layer AHB bus matrix is ​​used to establish parallel data channels between the processor, peripherals, and memory. The USB host and Ethernet MAC peripherals have dedicated DMA ports to achieve autonomous data transfer, while their APB peripherals are equipped with a peripheral DMA controller (PDC), so that bulk data transfers between memory and network interfaces occupy almost no processor resources. The Advanced Interrupt Controller (AIC) can handle a series of priority interrupt vectors within a specified number of processor cycles.

Figure 1 AT91SAM7X series upgraded to AT91SAM9XE series

Figure 2 AT91SAM9XE architecture

The cache enables the processor to obtain instructions and data in a timely manner at the speed it requires, unless the required data or instructions are not buffered in the cache. In this case, the processor has to idle for a while until the cache is refilled. The highly parallel DMA data transfer mechanism can reduce the processor's intervention in data transfer, but it is not completely non-involved. Because interrupt requests may occur at any time, even if only a few cycles are needed to process the interrupt. So how can we ensure that the system triggers a certain output based on a given input within the specified time?

How to get certainty

To achieve determinism, the code for each critical operation stored in flash memory can be broken down into modules less than 16Kb. The required module is loaded into the instruction cache and locked to ensure that it is always in the cache during the execution of the module. If necessary, the related data structures can also be loaded and locked in the data cache. Here, the latching function is implemented by the latch register of the cache. This ensures that the critical code is executed at the speed of the processor.

If a cache does not have the required instruction code, the cache will reload the required instruction code through the 128-bit data bus between it and the on-chip flash memory. The bus can load 32-bit data at 4 times the processor clock speed, greatly reducing the time to refresh the cache. In addition, the cache's wrapping function ensures that missed critical data is loaded first.

Taking all these factors into account, calculating the execution time, and making the worst-case scenario for multiple interrupts and DMA transfers at the same time, you can determine whether the real-time constraints can be met and with what margin. If necessary, you can also write some fallback procedures for each possible situation, allowing the system to run in a fail-soft mode (that is, a reliable but reduced performance mode) when the real-time requirements cannot be met.

in conclusion

Careful design of the application code to take advantage of the key architectural features of the processor core will enable near determinism in embedded connected real-time control systems based on complex control algorithms. These key architectural features include: data and instruction cache latching, wraparound capabilities, a 128-bit wide data bus connecting the cache to the on-chip flash memory, a low-latency advanced interrupt controller, and a DMA controller for direct data transfers between peripherals, network interfaces, and on-chip/off-chip flash memory.