Application and working principle of MAX813L in anti-interference of 51 single-chip microcomputer system

In recent years, single-chip microcomputers have been widely used in various industrial control, instrumentation, equipment, and product automation and intelligence due to their unique advantages such as small size, low price, and control orientation. At the same time, the reliability of single-chip microcomputer application systems has become an important topic that people are paying more and more attention to. There are many factors that affect reliability, such as the reliability of the components that constitute the system, the mutual coupling factors between the various parts of the system itself, etc. Among them, the anti-interference performance of the system is an important indicator of system reliability.

1 MAX813L chip and its working principle
1.1 Chip features
· Reset output when power is on, power is off, and the power supply voltage drops. The typical reset pulse width is 200 ms.
· Independent watchdog output. If the watchdog input is not triggered within 1.6 s, its output will become high.
· 1.25 V threshold detector, used for power failure alarm, battery low voltage detection, or power supply monitoring other than +5 V.
· Low-level effective manual reset input.
· 8-pin DIP package.
1.2 MAX813L pins and functions
1.2.1 MAX813L chip pin arrangement see Figure 1-1

1.2.2 Functions and working principles of each pin
(1) Manual reset input terminal
When the input low level is maintained for more than 140 ms, MAX813L outputs a reset signal. The minimum input pulse width requirement of this input terminal can effectively eliminate the jitter of the switch. Compatible with TTL/CMOS.
(2) Working power supply terminal (VCC): connected to +5V power supply.
(3) Power ground terminal (GND): connected to 0 V reference level.
(4) Power fault input terminal (PFI)
When the input voltage of this terminal is lower than 1.25 V, the signal at the output terminal of pin 5 changes from high level to low level.
(5) Power fault output terminal
When the power supply is normal, it maintains a high level. When the power supply voltage becomes low or the power is off, the output changes from high level to low level.
(6) Watchdog signal input terminal (WDI)
When the program is running normally, a pulse signal must be sent to this input terminal within a time interval of less than 1.6 s to clear the watchdog timer inside the chip. If the input terminal does not receive a pulse signal for more than 1.6 s, the internal timer overflows and pin 8 changes from high level to low level.
(7) When the reset signal output terminal (RST)
is powered on, it automatically generates a 200 ms reset pulse; when the manual reset terminal input is low level, this terminal also generates a reset signal output.
(8) Watchdog signal output terminal
The output remains high level during normal operation. When the watchdog output is on, the output signal of this terminal changes from high level to low level.

2 Circuit Design
2.1 Basic Working Principles
Most interference in industrial environments appears in the form of narrow pulses, and most of the phenomena that ultimately cause microcomputer system failures are "freezes". The reason is that when the CPU is executing a certain instruction, it is impacted by interference, causing its operation code or address code to change, causing the instruction to fail. At this time, the CPU executes randomly spelled instructions, and even executes operands as operation codes, causing the program to "run away" or enter a "dead loop". In order to automatically restore such "runaway" or "dead loop" programs and resume normal operation, an effective way is to use hardware "watchdog" technology. Use a watchdog to monitor the operation of the program. If the program "freezes", the watchdog generates a reset signal to guide the microcontroller program to re-enter normal operation.

In addition, the power supply voltage of the system is often unstable due to the input or withdrawal of many large-scale power-consuming equipment from the power grid at industrial sites. When the power supply voltage is reduced or the power is off, important data will be lost and the system cannot operate normally. If the microcontroller can quickly save important data before the power supply voltage drops to a certain limit, the loss will be minimized.
The circuit schematic diagram of the power-off working mode of the microcontroller is shown in Figure 2-1: When PD is set to 1, the power-off mode is activated, the output of the NAND gate is low, the clock generator stops working, all operating states in the microcontroller are stopped, and only the data in the on-chip RAM and SFR are saved. In the microcontroller system, the power supply voltage can be monitored with the help of certain external additional circuits, and the microcontroller can be notified in time when the power supply fails (such as by triggering an interrupt) to quickly save important data and disconnect the power supply of peripheral devices, so as to minimize the power consumption of the entire application system. When the power returns to normal, the power-off working mode is canceled, and the system resumes normal operation by resetting the microcontroller.

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2.2 Hardware Implementation Circuit Diagram
Figure 2-2 shows the typical application circuit diagram of MAX813L in the single-chip computer system. This circuit can realize automatic reset and manual reset at any time when power is on, instantaneous power off, and program runs "freeze"; and it can monitor power failure in real time to save data in time. This circuit
cleverly uses the manual reset input terminal of MAX813L. As long as the program runs away and causes the program to "freeze", the terminal level changes from high to low. When it changes to low for more than 140 ms, it will cause MAX813L to generate a 200 ms reset pulse. At the same time, the watchdog timer is cleared to 0 and the pin becomes a high level. The manual reset button can also be used at any time to make MAX813L generate a reset pulse. Since the low level is required to be maintained for at least 140ms to generate a reset pulse, the switch jitter can be effectively eliminated.
This circuit can monitor power failures (power failure, voltage reduction, etc.) in real time. One end of R1 in Figure 2-2 is connected to an unregulated DC power supply. When the power supply is normal, ensure that the voltage on R2 is higher than 1.26 V, that is, ensure that the PFI input level of MAX813L is higher than 1.26 V. When the power supply fails and the level of the PFI input is lower than 1.25 V, the power failure output level changes from high to low, causing the microcontroller to interrupt, the CPU responds to the interrupt, executes the corresponding interrupt service program, protects data, disconnects external power circuits, etc.

3 Anti-interference program design
3.1 Program running "freeze" and corresponding countermeasures
When the program runs normally, the main program periodically sends a pulse signal from P1.7 to the WDI input of MAX813L within a time interval of less than 1.6 s to clear the watchdog timer inside the chip. The implementation instruction is:
RST-PRG: SETB P1.7
NOP
CLR P1.7
If the input does not receive a pulse signal for more than 1.6 s, the internal watchdog timer overflows and pin 8 changes from high level to low level. This causes MAX813L to generate a 200 ms reset pulse. At the same time, the watchdog timer is cleared to 0 and the pin becomes high level.
It should be noted that after the entire microcontroller system is reset, the entire program will restart the initialization operation from address 0000H under the guidance of the PC pointer, which is not allowed in many cases (such as continuous process flow), so corresponding measures must be taken. First, after the reset of the single-chip computer system, the program should first determine whether it is booting (cold start) or reloading after a "freeze" during operation (hot start). Because in general, in these two startup modes, the work that the system program needs to do before entering the main process is often different. For example, after a cold start, the system program often needs to self-check the system resources and set each peripheral device to the corresponding standby state in the initialization program. After a hot start, the system resources are often no longer self-checked, and the settings of each peripheral device should be avoided as much as possible. Only some necessary settings are made for some resources of the single-chip computer system itself. Secondly, in most cases, we can always decompose a continuous process and turn it into a continuous process composed of independent sub-processes (states). During the operation of the main program, the corresponding state and the relevant parameters in the state are saved in time. In this way, when the program runs and the system is reset and initialized under the action of MAX813L, the state parameters saved in advance will be queried first, and then the flow of the program will be determined based on this parameter. At the same time, the parameters saved in advance in this state are taken out, and the necessary recovery settings are made for the system peripheral devices and the boot program continues to run. The system program flow chart designed based on this idea is shown in Figure 3-1.
3.2 Power failure and corresponding countermeasures
When the power fails, it causes the microcontroller to interrupt, the CPU responds to the interrupt, executes the corresponding interrupt service program, protects data, disconnects the external power circuit, etc. In order to achieve this, the interrupt priority (PX0) must be set to the highest, especially when there are other interrupts in the system. The interrupt priority setting can be achieved through the interrupt priority register IP. In addition, the total enable bit (EA) of the interrupt enable register IE and the external interrupt 0 interrupt enable bit (EX0) must be set. The implementation instructions are:

SETB IP．0 ；Set PX0＝1
SETB IE．7 ；Set EA＝1
SETB IE．0 ；Set EX0＝1

As for the triggering mode of the interrupt source. If the level trigger is selected, an auxiliary circuit must be added when the interrupt is erased, otherwise the interrupt cannot be executed normally; if the jump trigger is selected, when a negative jump occurs at the end, the CPU internal hardware automatically sets the interrupt flag IE0, the CPU responds to the interrupt, and IE0 is cleared by the hardware when the interrupt service program is transferred through the vector address. Therefore, based on the above analysis, the jump trigger mode must be selected. The trigger mode is determined by the IT0 bit in the timer control register TCON. The implementation instruction is:
SETB TCON． 0
Designing a good interrupt service program is of great significance for the continuous and reliable operation of the system. In the interrupt service program, first save important data to the on-chip RAM (powered by the backup power supply when power is off, the corresponding implementation circuit is not drawn). Send a control signal to disconnect the peripheral device, and finally set the PD position of the power control register PCON to 1, activate the power-off working mode, and the interrupt returns. The interrupt service program is implemented as follows (where R0 represents the buffer address of the saved data in the memory, DPTR represents the buffer address of the data to be saved in the external RAM, and R1 represents the number of bytes of data to be saved):
INT0: MOVX A, @DPTR; save data
MOV @R0, A
INC R0; memory buffer pointer plus 1
INC DPTR; external memory buffer pointer plus 1
DJNZ R1, INT0; save completed? Not finished, continue saving
SETB PCON. 1; activate power-down mode
RET1

4 Conclusion
This system cleverly uses the MAX813L chip to realize the watchdog circuit, power failure monitoring circuit and manual and automatic reset circuit of the single-chip system. The circuit structure is compact and the design is reasonable. Combined with the program anti-interference design scheme given in this article, it can effectively solve the "freeze" phenomenon and the adverse effects of power failure during program operation. The actual operation in the real-time monitoring system of the gallium nitride semiconductor thin film growth process designed by us shows that: the scheme is reasonably designed, reliable in operation, strong in anti-interference ability, and has achieved satisfactory use results, and can be promoted and applied to other single-chip control systems.