Design of a logic non-circulating reversible speed regulation system based on 51 single chip microcomputer

Here is a design of a logic non-circulating reversible speed control system based on a single-chip microcomputer. The system design adopts a fully digital circuit to realize functions such as digital pulse triggering, digital speed setting detection and digital PI algorithm. The speed and current regulation, logical judgment and complex calculations are realized by software. It has optimization, self-adaptation, nonlinearity, intelligence and other control laws that are different from general analog circuits, and it is flexible and convenient to change.

2 System composition and control principle

2.1 System composition

The digital logic non-circulating reversible speed regulation system is realized by AT89C51 single chip microcomputer to realize double closed loop control, non-circulating logic control, trigger pulse formation and phase control, as shown in Figure 1. In Figure 1, ASR is the speed loop, ACR is the current loop, DLC is the non-circulating logic controller, GT is the trigger pulse, TA is the voltage transformer, TG is the speed generator, and M is the DC motor. The main circuit adopts two groups of thyristor devices, positive group VF and reverse group VR, which are anti-parallel. The control circuit adopts the speed ASR and current ACR double closed loop system.

2.2 Control Principle

Digital non-circulating current logic control selects the positive or negative group of thyristors according to the positive or negative output value of the speed regulator, and switches accordingly according to whether the current of the main circuit is zero. And the working status of the working group is memorized. Through torque polarity detection and zero current detection, corresponding logical judgment is made to release one group of thyristors and lock the other group of thyristors. For this purpose, two storage units L1 and L2 are set in the single-chip computer to memorize the working status of the positive group thyristor vF and the negative group thyristor VR.

3 System Hardware Design

The system hardware design is based on the AT89C51 single-chip microcomputer, and consists of program memory EPROM, address latch, A/D converter, 2 programmable counters, timer, pulse widening, photoelectric isolation, pulse amplification, zero-crossing detection and wave edge detection circuits, as shown in Figure 2.

3.1 Triggers

The main transformer and the synchronous transformer are both connected as D/Y-11. The symmetrical three-phase AC synchronous voltage lags 30° after the RC phase shift. The zero crossing point of the AC waveform is aligned with the trigger delay angle α=0°, and the trigger pulse can only be generated between 0° and 180°. The three-phase AC voltage after the RC phase shift is converted into a three-phase square wave with a difference of 120° and a width of 180° through the zero detector, which is added to the P1.0, P1.1 and P1.2 pins of the microcontroller as the detected power state, and this state is used as the basis for pulse distribution to determine the trigger sequence of VR and VF. The square wave outputs a negative pulse with an interval of 60° through the wave edge detector as the external interrupt request signal of the microcontroller. The three-phase transformer generates 6 interrupt signals in each cycle, and completes the pulse formation, distribution and shift control in each interrupt service program.

3.2 PI Regulator

The control law of the PI regulator is:

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In the formula, y(t) is the output of the PI regulator; e(t) is the input of the PI regulator; Kp is the proportional coefficient; T1 is the integral time constant.

After discretizing equation (1), the regulator output increment between the (k-1)th and kth sampling times is △y(k):

In the formula, △e=ek-ek-1; yk is the kth output of the PI regulator; yk-1 is the (k-1)th output of the PI regulator; ek is the deviation between the given value and the feedback value at the seventh sampling; ek-1 is the deviation between the given value and the feedback value at the k-1th sampling; KI is the integral coefficient,

The difference equation obtained from formula (5) is:

In the formula, KI=Kp-K2, K2=TKI; yn is the nth sampling output; △Un is the input deviation at the nth sampling. In order to improve the accuracy, PI operation uses double bytes.