ADC application elements in C8051F020

C8051F020 (referred to as F020) is a mixed-signal SOC 8-bit microcontroller launched by Cygnal Company of Texas, USA. It belongs to the F02x sub-series in the C8051F series. Its performance-price ratio is extremely competitive in current application fields. F020 has 8-channel 12-bit A/D conversion (referred to as ADC) interface and 8-channel 8-bit in-circuit programmable (ISP) ADC circuit. There are 15 special function registers (referred to as SFR) on the chip related to the control of the ADC. They are :

AMUX0SL——AMUX0 channel selection register, reset value is 00000000;

MAX0CF——AMUX0 configuration register, reset value is 00000000;

ADC0CF——ADC0 configuration register, the reset value is 11111000;

ADC0CN——ADC0 control register, the reset value is 00000000;

ADC0H——ADC0 data word MSB register, the reset value is 00000000;

ADC0L——ADC0 data word LSB register, the reset value is 00000000;

ADC0GTH——ADC0 lower limit data high byte register, the reset value is 11111111;

ADC0GTL——ADC0 lower limit data low byte register, the reset value is 11111111;

ADC0LTH——ADC0 upper limit data high byte register, the reset value is 00000000;

ADC0LTL——ADC0 upper limit data low byte register, the reset value is 00000000;

AMX1SL——AMUX1 channel selection register, the reset value is 00000000;

ADC1CN——ADC1 control register, the reset value is 00000000;

ADC1CF——ADC1 configuration register, the reset value is 11111000;

ADC1——ADC1 data word register, the reset value is 00000000;

REF0CN——Reference voltage control register, reset value is 00000000.

ADC is an important function of a mixed-signal controller. If you want to be proficient in application programming, you must have a clearer overall understanding of its related elements.

1 ADC accuracy and channels

F020 is packaged in TQFP100. The chip has 8 pins (pins 18 to 25) dedicated to analog input and is the input terminal of 8-channel 12-bit ADC. The conversion accuracy of each 12-bit channel is its own ±1LSB (lowest bit). In fact, there is only one 12-bit Successive Approximation Register (SAR) ADC, and between it and each input there is a multiplexer with 9-channel inputs (configurable analog multiplexer AMUX). The 9th channel of AMUX is connected to the temperature sensor. In F020, the 12-bit ADC is called ADC0, and the 8-channel 8-bit in-system programmable (ISP) ADC circuit is called ADC1. Its 8 external pins are multiplexed with the P1 port, and the on-chip structure is similar to ADC0, except that the number of conversion bits is 8 bits, and the conversion accuracy is 8 bits ±1LSB.

Each pair of ADC0 ports can be programmed to be individually single-ended or differential. The port pairing for differential input is 0-1, 2-3, 4-5, 6-7. This setting is determined by the lower 4 bits of the channel selection register AMUX0SL and the lower 4 bits of the channel configuration register AMUX0CF. In AMX0CF, bits 3 to 0 each correspond to 2 pin channels. Bit value = 0, indicates an independent single-ended input (reset values ​​are all single-ended inputs); bit value = 1, indicates a differential input pair. When differential input is selected for AMX0CF, it is only valid when selecting even-numbered (including 0) channels in AMUX0SL (Note: When the lower 4 bits of AMUX0SL are 1xxx, the temperature sensor is selected regardless of the value of the lower 4 bits of AMX0CF).

When bit 3 of REF0CN is set to "1", the temperature sensor is allowed to be used; when set to "0", the output of the temperature sensor is in a high-impedance state. The value of the temperature sensor can be used to correct the nonlinearity of the parameters or to record and adjust temperature-related data.

2 ADC rate and startup

The speed of the ADC in the C8051F series microcontroller can be programmed, but at least 16 system clocks are used. Generally, a tracking/hold capture time of 3 system clocks (>1.5 μs ) is automatically added before conversion. The method of setting the ADC rate in F020 is through bits 7~3 of the configuration register ADCxCF (x is 0 or 1), and its reset value is 11111 (bits 7~3=SYSCLK/CLK SAR-1).

Generally, the ADC must be in tracking mode before starting. If bit 6 of the control register ADCxCN is "0", it will always be in tracking mode (at this time, starting the 4 startup modes can be 3 system clocks faster than tracking startup); if it is " 1", there are 4 tracking start methods to choose from, that is, assigning values ​​to bits 3~2 in ADCxCN: 00 is tracking when writing 1 to ADBUSY (software command); 01 is timer 3 overflow tracking; 10 is the rising edge of CNVSTR Tracking (external signal); 11 is timer 2 overflow tracking.

At reset, Bit 7 of ADCxCN is 0 and is in the shutdown state. At the end of each conversion, bit 5 of ADCxCN is "1", and the falling edge of bit 4 (busy flag) triggers a structural interrupt. These status bits can also be queried by software.

3 ADC reference and gain

The F020 has a 1.2V, 15×10 -6/℃ bandgap voltage reference generator and a twice-gain output buffer on-chip. The 2.4V reference voltage (VREF) can be connected to ADC0, ADC1 and DAC through external pins. The external load capacity of VREF is 200 μA (it is recommended to connect a load resistor to ground when driving an external load). When the ADC uses bias, bit 1 in the reference source control register REFcCN must be set to "1"; if "0", the internal bias is turned off. At this time, the external reference voltage can be used through the VREF pin (pin 12). The external reference voltage must be less than VAV±0.3V (and greater than 1V). When neither ADC nor DAC is used, bit 0 of REFxCN can be set to "0" to put the buffer amplifier in power saving mode (the output is in a high impedance state).

When bit 4 of REF0CN is set to "0", ADC0 is biased with VREF, and when it is "1", DAC0 output bias is used; when bit 3 of REF0CN is set to "0", ADC1 is biased with VREF, which is "1" When, use AV+bias.

In the ADC circuit of F020, there is an internal amplifier (PGA) with programmable gain behind the input multiplexer AMUX. This is particularly useful when there is a large difference in the input voltage signal range between analog channels, or when a signal with a large DC offset needs to be amplified (in differential input mode, DAC can be used to provide DC offset). The setting method is to configure bits 2~0 in ADCxCF (000 corresponds to the PGA gain of 1; 001 corresponds to 2; 010 corresponds to 4; 011 corresponds to 8; 10x corresponds to 16, 11x corresponds to 0.5). The gain here also works on the temperature sensor signal. When the gain is 1, VTEMP=0.002 86(V/℃)(TEMPC) ℃+0.776V.

4 ADC data and control

Corresponding to single-ended input, the ADC result data word format is: 0V——0000, VREF——0FFF or FFF0.

Corresponding to differential input, the ADC result data word format is 2's complement: VREF——07FF, 0——0000, -VREF——F800 or 8000.

Setting Bit 0 of ADCxCN to "0" causes the result to be right-justified; setting "1" to "1" causes the result to be left-justified. When input is differential, the extra high bits produced by right justification are sign extension bits.

The C8051F series microcontroller also has a data-related window interrupt generator or programmable window detector, also called the ADC upper (lower) limit data register ADC0G (L) TH (L), which monitors a key voltage in the background. When the conversion data is within (or outside) the specified window, apply for a conversion end interrupt to the controller. When it is required to interrupt within the window, the upper limit register LT is loaded with the high-order window number, and the lower limit register GT is loaded with the low-order window number; if it is required to interrupt outside the window, the lower limit register GT is loaded with the high-order window number, and the upper limit register GT is loaded with the high-order window number. The lower limit number of windows loaded into LT.

When reset, the status of the ADC part is: the internal voltage reference buffer is closed, the internal bias voltage is closed, the internal sensor is closed, the ADC is disabled, the conversion result data register is right-aligned, the 12-bit ports are all single-ended inputs, and the port points to AIN0, SAR Convert 33 system clocks, the internal amplifier gain is 1, the lower limit data register is FFFFH, and the upper limit data register is 0000H.

Based on various factors related to ADC in F020, in order to correctly apply the ADC function, you should program in the following order: Set reference voltage>Set to allow ADC>Set tracking (starting) mode>Set data alignment>Configure channel>Select channel>Settings Convert clock and gain > Set window detection upper and lower limits > Start conversion. The sequence of operating SFR (taking 12 bits as an example) is: REF0CH>ADC0CN>AMX0C>AMUX0SL>ADC0CF>ADC0GTH>ADC0GTL>ADC0LTH>
ADC0LTL>ADC0CN or other startup methods.