Implementation of multi-waveform radar signal generator based on AD9957

The implementation scheme of multi-waveform radar signal generator based on AD9957 discussed in this paper integrates multiple technologies such as RS 232 serial communication, FPGA and DDS. It has the characteristics of digitalization, multi-function and programmability, and has made some exploration and experimental research in modular design.

1 Overall solution design

Figure 1 is the overall structure diagram of the multi-waveform radar signal generator. The system mainly consists of three parts: PC software, waveform control and waveform generation. The circuits of each part in Figure 1 are briefly described as follows.

(1) PC software programming. Use VC to write the human-computer interaction interface and use it to call the data generated by Matlab.

(2) Reset circuit: The power-on reset or manual reset circuit of the waveform generator is used to initialize the waveform generator upon power-on or manually initialize the waveform generator.

(3) Waveform database memory RAM: The waveform database memory stores all waveform data required by the project and provides the waveform generator with the required waveform data.

(4) UART transceiver. Complete the communication between PC and FPGA.

(5) Power supply circuit: Provides the necessary power for the waveform generator and waveform control module.

(6) Waveform control module: The waveform control module receives the control signal input from the interface circuit, completes the waveform data configuration of the waveform generator according to the system requirements, and outputs the required waveform signal.

(7) Waveform generator. The waveform generator is the waveform signal source of the signal generator.

(8) FPGA device configuration and programming circuit: FPGA device configuration and programming completes the data programming and configuration of the FPGA device.

(9) Clock circuit: Provides working clock for the waveform generator and FPGA.

2 Introduction to main functional modules

2.1 Introduction to the digital quadrature up-conversion chip AD9957

AD9957 is a digital quadrature up-conversion integrated circuit produced by Analog Devices Inc. of the United States with 18-bit I, Q data and channels and built-in 14-bit D/A converter. AD9957 has a 32-bit phase accumulator; built-in 1 024×32 b RAM, which can realize internal modulation function; internally powered by 1.8 V and 3.3 V, ultra-low power consumption; built-in low-noise reference clock multiplier allows low-cost, low-frequency external clock to be used as system clock, while still providing excellent dynamic performance. AD9957 has 3 working modes: quadrature modulation mode, single-frequency output mode, and interpolation DAC mode.

2.2 UART transceiver design

In this paper, the communication between PC and FPGA internal RAM is completed through UART transceiver. Figure 2 is the top-level schematic diagram of the UART transceiver designed by FPGA, which mainly consists of uartrx (receiving module) and uarttx (transmitting module). While completing the data transmission, the correctness of the data received by FPGA can be checked through the serial port debugging program integrated into the Matlab human-computer interface, which can simplify the program debugging process.

2.3 Waveform Control Module

At present, waveform controllers are usually implemented using three methods: single-chip microcomputers, field programmable gate array devices, and DSP. Based on comprehensive considerations of system timing control requirements, circuit changes and operational reliability, development costs and cycles, FPGA is selected in the design to implement the waveform control circuit. FPGA can not only solve the problems of miniaturization, low power consumption, and high reliability of electronic systems, but also has a short development cycle, low investment in development software, and can be reprogrammed. Figure 3 is the waveform control module of AD9957. Among them, M1 and MO are mode control codes, F[2..O] is the work area selection code, S_CLK is the serial port clock, and S_DATA is the serial port data. Figure 4 is the simulation timing diagram of the AD9957 control module. It can be seen from the figure that S_DATA and S_CLK are one-to-one corresponding.

3. Software Modular Design

3.1 Design Process

Figure 5 shows the DDS design process that is currently used. First, the waveform data must be designed according to the system requirements and stored in a file in a certain format. Then, the RAM is designed using FPGA design software (Quartus, etc.). The corresponding data of the RAM is specified as the designed waveform data file, and finally the data is configured into the DDS using logic. If the waveform data needs to be modified, the above steps need to be performed once. If it is modified multiple times, it is relatively cumbersome.

Figure 6 shows the baseband waveform data generation process used in this design. By inputting waveform parameters, sampling rate and other data in the software interface, the software algorithm is used to generate data and send the data to the RAM built into the FPGA. Under the control of the FPGA input control signal, the sampled data is sent to the DDS chip.

3.2 PC Software

The PC application software completes all operations related to waveform data and data communication functions with the hardware. Figure 7 shows the interface of the application software based on Matlab GUI, which includes the following functions:

(1) Waveform data generation. The signal with the specified waveform form, pulse width, bandwidth and other parameters is simulated, including the operation of time domain waveform data and spectrum analysis, display, and data saving. Currently, LFM, NFLM, phase encoding and triangle wave signal forms can be generated, and arbitrary waveforms can be added if necessary.

(2) Computer data communication. The computer serial port is connected to the system motherboard to realize asynchronous serial data communication based on RS 232 interface. The interface is simple and easy to configure. The purpose is to realize the download and verification of the required waveform data from the computer to the waveform generation hardware memory.

(3) User software interface. This interface can complete waveform selection; time width, bandwidth, sampling rate, intermediate frequency setting; signal time domain waveform, frequency-time relationship display; baseband sampling data generation and downloading and other functions.

(4) Portability. The M file of the human-machine interface compiled based on Matlab can be converted into different types of source code such as C or C++ by the Matlab compiler (cornpiler), and then generate an application file that can run independently according to the needs. It does not require the support of the Matlab environment, which greatly expands the application scope of the program. At the same time, after the M file is compiled, the running speed is greatly improved.

4 Experimental Results

Figure 8 shows the spectrum of AD9957 working in single frequency output mode, system clock 1 GHz, 0 dBm, output 185 MHz point frequency, and its spurious is better than -70 dBc. Figure 9 shows the spectrum of nonlinear FM signal with bandwidth 10 MHz and time width 20 μs when AD9957 works in quadrature modulation mode. Due to space limitations, linear FM, phase coding and other signals are not listed here one by one.

5 Conclusion

This design mainly discusses a method for implementing radar signals based on DDS. The system design combines software with hardware, making the operation simple and flexible, and making the software portable. The Matlab programming interface enables the operator to modify data quickly and easily. The experimental results prove the correctness of the implementation method of the multi-waveform radar signal generator based on AD9957. Due to the low rate of asynchronous communication data transmission and the limited capacity of FPGA built-in ROM, if a higher speed data transmission is required between PC and RAM, it can be considered to switch to PCI bus or computer network port transmission; when a large width signal or a large amount of sampled data is required, it exceeds the internal memory capacity of the single-chip FPGA, and a large-capacity chip or external storage device can be used instead.