Design of turret azimuth test system based on C8051F040

1 Introduction
With the development of military technology, the informatization of test systems is the main way to realize the modernization of our military equipment. It is imperative to use high-tech to improve the performance of old equipment. This is not only an important link in improving existing weapons and equipment, but also an important factor in maximizing the overall combat effectiveness of existing equipment. Among the turret azimuth systems currently in service in China, there are many old models, most of which are not equipped with automatic detection and recording equipment. The calculation of various parameters of the turret azimuth system, data processing and reporting are mostly done manually, which is difficult to be competent for fast and accurate collection in complex environments. In order to meet the requirements of modern turret azimuth systems, a complete test system with automatic collection and analysis capabilities must be available.

2 Introduction to the main components
2.1 C8051F040 MCU
C8051F040 is a fully integrated mixed signal system-on-chip MCU. The core adopts the high-speed, pipelined 8051-compatible CIP-51 core; controller area network (CAN2.OB) controller with 32 message objects, each with its own identifier; 8-bit 500 Ks/s MI) converter with PGA and 8-channel analog multiplexer; 64KB in-system programmable Flash memory: with SPI, SMBus, I2C interface and 2 UART serial interfaces; VDD monitor, watchdog timer and clock oscillator. A truly independent system-on-chip: the on-chip JTAG debugging circuit allows the use of the product MCU installed in the final application system for non-intrusive (without occupying on-chip resources), full-speed, in-system debugging. The debugging system supports observing and modifying memory and registers, and supports breakpoints, watchpoints, single-stepping, and run and stop commands. When using JTAG debugging, all analog and digital peripherals can operate with full functionality; each MCU can operate within the industrial temperature range (-45°C to +85°C) and the operating voltage is 2.7 to 3.6 V. The port I/O, RST and JTAG pins all allow 5 V input signal voltage.
2.2 CAN controller SJA:1000
The interior of SJA1000 is mainly composed of interface management logic IML, information buffer (including transmit buffer TXB and receive buffer RXFIF0), bit stream processor BSP, receive filter ASP, bit timing processing logic BTL, error management logic EML, internal oscillator and reset circuit. IML receives commands from the CPU, controls the addressing of CAN registers and provides interrupt information and status information to the control. The CPU controls the data to be sent to TXB through IML, and the data in TXB is processed by BSP and output to the CAN bus through BTL. BTL always monitors the CAN bus. The receiving process is started when the conversion of the effective information header "hidden level to control level" is detected. The received information is first processed by the bit stream processor BSP and filtered by the ASP. Only when the identification code of the received information matches the ASP check, the received information is finally written into the RXB or RXFIIFO. The RXFIFO can cache up to 64 bytes of data, which can be read by the CPU. The EML is responsible for the error control of the modulator in the transmission layer. It receives the error report of the BSP and prompts the BSP and IML to perform error statistics.
2.3 CAN transceiver PCA82C250
PCA82C250 is a highly integrated independent controller for the industrial environment controller area network (CAN). It has all the necessary features required to complete the high-performance communication protocol. It has a simple bus that can complete all the functions of the physical layer and the data link layer. The application layer of the electronic control unit (ECU) is provided by the microcontroller. PCA82C250 can reduce the wire setting in the application of general industrial environment and enhance the diagnosis and monitoring capabilities. Its main features: multi-master structure, can connect various types of microcontroller interfaces, bus access priority (depending on the message identifier), 2032 message identifiers, guaranteed waiting time for high priority messages, powerful error handling capabilities, 0 to 8 bytes data length, configurable bus interface, grouping and broadcast message functions, lossless structured bit-by-bit arbitration, non-return-to-zero encoding/decoding with bit filling function, programmable transmission rate, and clock frequency of 16 MHz.

3 System Design
The turret azimuth test system mainly collects and processes the position signals generated by the synchro and the rotary transformer; and outputs the position information in real time through the LED display and the CAN bus. Figure 1 is a block diagram of the system structure, which mainly includes the main control module, 2-way SDC data acquisition circuit, LED display module, CAN communication module, etc.

3.1 Hardware circuit design
Figure 2 is a block diagram of the hardware circuit design. The hardware circuit design of this system is based on the C8051F040 single-chip microcomputer, using 16ZSZ/XSZ-02 (16-bit continuous tracking synchro/resolver-to-digital converter) acquisition unit, SJAl000CAN controller plus drive controller PCA80C250 as the communication system.

In order to enhance the anti-interference ability of the control node and prevent crosstalk between lines, SJAl000 is connected to PCA82C250 through an optocoupler 6N137, so that each CAN node on the bus is isolated to protect the CAN controller. PCA82C250 is a CAN bus transceiver, an interface device between the CAN controller SJAl000 and the CAN bus, and transmits the CAN bus in a differential manner. Its pin RS is used to select the working mode of PCA82C250 as high speed, slope control or waiting. Pin. RS is grounded, PCA82C250 is in high-speed mode: Pin RS is connected in series with a 15~200 kΩ resistor R and then grounded, which is used to control the rising and falling slopes to reduce radio frequency interference. Pin RS is connected to a high level, and PCA82C250 is in waiting mode. At this time, the transmitter is turned off, the receiver is in a low current working state, and can respond to the dominant bit on the bus. If PCA82C250 is at the network terminal of CAN bus, a 120Ω matching resistor must be added to the bus interface part to protect PCA82C250 from overcurrent shock. Generic-Array Logic GAL (Generic-Alray Lbgic) is a new type of electrically erasable and programmable PLD device. In this system, it is mainly used to form a decoding circuit to realize the chip selection of SJAl000. The main control circuit is shown in Figure 3.

3.2 Software Implementation
The software functions of this system mainly include five parts: data transmission module, data display module, data acquisition module, data processing module, and exception handling module, as shown in Figure 4. Among them, the data display module mainly completes the display of the real-time azimuth data of the synchro, the display is 6 bits, and the resolution is 0.01 digits; the data processing module mainly completes the coarse and fine synthesis and error correction functions; the data acquisition module mainly completes the binary angle encoding of the coarse and fine SDC channel values; the data transmission module mainly completes the data reception and transmission through the CAN bus; the exception handling module mainly completes the software reset of the entire system after the system is abnormal.

The system software design mainly realizes the functions of turret azimuth data acquisition, data processing, data display and CAN communication. After the system is initialized, the synchronization signal type (internal synchronization or external synchronization) is selected first, and then two SDC signals are received simultaneously. The two SDC data are combined and corrected according to the combination algorithm, and finally displayed in real time through LED, and the azimuth data is transmitted to the external device in real time through CAN. The software flow chart is shown in Figure 5.

4 Conclusion
The turret azimuth test system is based on the C8051F040 single-chip microcomputer, which realizes the offline detection of the synchro and the rotary transformer, greatly improving the test efficiency. The test system has the advantages of simple structure, small size, and high reliability. The test proves that the detection system works stably, has strong anti-interference ability, is easy to operate, and has high precision. Therefore, the system is reasonably designed and has good use value.