High-speed ADC power supply design

Many applications today require high-speed sampling analog-to-digital converters (ADCs) with 12-bit or higher resolutions to enable users to make more accurate system measurements. Unfortunately, higher resolution also means that the system is more sensitive to noise. For every bit increase in system resolution, such as from 12 to 13 bits, the system sensitivity to noise doubles. Therefore, for ADC designs, designers must consider an often forgotten source of noise - the system power supply. ADCs are sensitive devices, and to achieve the best performance ratings stated in the data sheet, all inputs, such as analog, clock, and power, should be treated equally. Noise comes from many sources and in many forms, and noise radiation can affect performance.

The buzzword in today's electronics industry is that new designs should be "green" while reducing costs. Specifically for portable applications, it requires reducing power consumption, simplifying thermal management, maximizing power efficiency, and extending battery life. However, most ADC data sheets recommend using linear power supplies because they have lower noise than switching power supplies. This may be true in some cases, but new technological advances have proven that switching power supplies can also be used in communications and medical applications.

This article describes various test measurements that are critical to understanding high speed ADC power supply design. To determine the converter's sensitivity to the effects of power rail noise, and to determine at what noise level the rail must be for the ADC to achieve expected performance, two tests are useful: generally referred to as the power supply rejection ratio (PSRR) and the power supply modulation ratio (PSMR).

What is Power Supply Rejection?

There are two main factors that determine the performance of the ADC when there is noise on the power rail: PSRR-dc, PSRR-ac, and PSMR. PSRR-dc refers to the ratio of the change in power supply voltage to the resulting change in ADC gain or offset error. It can be expressed as a fraction of the least significant bit (LSB), a percentage, or logarithmic dB (PSR = 20 × log10 (PSRR)), and is usually specified using DC conditions.

However, this method only reveals how one of the ADC's rated parameters may vary with supply voltage, and therefore does not demonstrate converter stability. A better approach is to actively couple the signal (noise source) through the converter circuit by applying an AC signal on top of the DC supply and then testing the power supply rejection (PSRR-ac). This method essentially attenuates the converter, presenting itself as a spur (noise) that rises above the converter's noise floor at a given amplitude. The significance of this is to show when the converter will break down given the injected noise and amplitude. It also gives the designer an idea of ​​how much power supply noise will affect or add to the signal. PSMR affects the converter in a different way, and it shows the converter's sensitivity to the effects of power supply noise when modulated with the applied analog input signal. This effect manifests itself as modulation near the IF frequency applied to the converter, and can severely corrupt the carrier sidebands if the power supply design is not careful.

In summary, power supply noise should be tested and treated like any other input to the converter. The user must be aware of system power supply noise or it will raise the converter noise floor and limit the dynamic range of the entire system.

Power Power supply test

Figure 1 shows the setup for measuring the ADC PSRR on a system board. Measure each supply individually to better understand the dynamic behavior of the ADC when an AC signal is applied to the supply under test. Start with a high value capacitor, such as a 100uF non-polarized electrolytic capacitor. Use a 1mH inductor to act as an AC block for the DC supply, commonly called a "bias-T," which can be purchased in a connectorized package.

To measure the amplitude of the AC signal using an oscilloscope, place one of the scope probes on the power pins where the power goes into the ADC under test. To simplify, define the amount of AC signal applied to the power supply as a value relative to the full scale of the converter input. For example, if the full scale of the ADC is 2Vpp, use 200mVpp or -20dB. Next, with the input of the converter grounded (no analog signal applied), look for the error spur at the test frequency in the noise floor/FFT spectrum, as shown in Figure 2. To calculate the PSRR, simply subtract –20dB from the error spur value shown on the FFT spectrum. For example, if the error spur appears at -80dB of the noise floor, the PSRR is -80dB - (-20dB), or -60dB (PSRR = Error Spur (dB) - Oscilloscope Measurement (dB)). A value of -60dB may seem unusual, but converted to voltage, it is equivalent to 1 mV/V (or 10-60/20), a number that is not uncommon for a PSRR specification in any converter data sheet.

The next step is to vary the frequency and amplitude of the ac signal to characterize the PSRR of the ADC in the system board. Most of the values ​​in the data sheet are typical values ​​and may only be for the worst operating conditions or the worst performing power supply. For example, the +5 V analog supply may be the worst relative to the other supplies. Make sure that all power supplies are characterized and consult the factory if they are not. This will allow the designer to set appropriate design constraints for each supply.

Keep in mind that there is a drawback when using an LC configuration to test PSRR/PSMR. When sweeping the frequency band of interest, the signal level required at the waveform generator output to achieve the desired input level at the ADC power pins may be very high. This is because the LC configuration forms a notch filter at a certain frequency (depending on the values ​​selected). This can significantly increase the ground current at the notch filter, which can enter the analog input. To correct this, simply swap in new LC values ​​when the test frequency causes measurement difficulties. It should also be noted here that the LC network also has losses at DC. Remember to measure the DC supply at the ADC's power pins to compensate for this loss. For example, a +5V supply may only have +4.8V on the system board after passing through the LC network. To compensate for this loss, simply increase the supply voltage.

PSMR is measured in essentially the same way as PSRR. However, when measuring PSMR, an analog input frequency is applied to the test setup, as shown in Figure 3.

Another difference is that the modulation or error signal is only applied at a low frequency in order to observe the mixing effect of this signal with the analog input frequency applied to the converter. For this test, frequencies between 1-100kHz are commonly used. As long as the error signal, or the product of mixing, can be seen around the fundamental frequency, the amplitude of the error signal can be kept relatively constant. However, it is also useful to vary the amplitude of the applied modulation error signal to check to ensure that this value is constant. For the final result, the difference in amplitude of the highest (worst) modulation spur relative to the fundamental frequency will determine the PSMR specification. Figure 4 shows an example of a measured PSMR FFT spectrum.

Power supply noise analysis

For the converter and the final system, it is important to ensure that the noise on any given input does not affect the performance. Now that PSRR and PSMR have been introduced and their importance, an example will be given to illustrate how the measured values ​​can be applied. This example will help designers understand what to pay attention to and how to design correctly in order to understand the power supply noise and meet the system design requirements.

First choose the converter, then the regulator, LDO, switching regulator, or something else. Not all regulators are suitable. You should check the noise and ripple specifications in the regulator data sheet, as well as the switching frequency (if using a switching regulator). A typical regulator may have 10 μV rms noise in a 100 kHz bandwidth. Assuming this noise is white, it equates to a noise density of 31.6 nVrms/rt-Hz in the frequency band of interest.

Next, check the converter’s power supply rejection to understand when the converter’s performance will degrade due to power supply noise. Most high-speed converters typically have a PSRR of 60 dB (1 mV/V) in the first Nyquist zone of fs/2. If the data sheet does not give this value, measure it as described above or ask the manufacturer.

Using a 16-bit ADC with a 2Vpp full-scale input range, 78dB SNR, and a 125MSPS sampling rate, the noise floor is 11.26 nVrms. Noise from any source must be below this value to prevent it from affecting the converter. In the first Nyquist zone, the converter noise will be 89.02 μV rms (11.26 nVrms/rt-Hz) × sqrt(125MHz/2). Although the regulator noise (31.6 nV/rt-Hz) is more than twice that of the converter, the converter has a 60dB PSRR, which suppresses the switching regulator noise to 31.6 pV/rt-Hz (31.6 nV/rt-Hz × 1 mV/V). This noise is much smaller than the converter noise floor, so the regulator noise will not degrade the converter performance.

Power supply filtering, grounding, and layout are also important. Adding 0.1μF capacitors to the ADC supply pins can reduce the noise below the calculated values ​​above. Keep in mind that some supply pins draw more current or are more sensitive than others. Therefore, decoupling capacitors should be used judiciously, but be aware that some supply pins may require additional decoupling capacitors. Adding a simple LC filter to the power supply output can also help reduce noise. However, when using a switching regulator, cascading filters can suppress the noise to a lower level. It is important to remember that each additional stage of gain increases the gain by about 20dB per decade.

Finally, it is important to note that the above analysis is for a single converter. If the system involves multiple converters or channels, the noise analysis will be different. For example, ultrasound systems use many ADC channels that are digitally summed to increase the dynamic range. The basic principle is that the noise floor of the converter/system decreases by 3dB for every doubling of the number of channels. For the above example, if two converters are used, the noise floor of the converter will be halved (-3dB) and if four converters are used, the noise floor will be -6dB. This is possible because each converter can be treated as an uncorrelated noise source. Uncorrelated noise sources are independent of each other and therefore can be RSS (root sum of squares) calculated. Ultimately, as the number of channels increases, the noise floor of the system decreases, the system becomes more sensitive, and the design constraints on the power supply become tighter.

Conclusion

It is impossible to eliminate all power supply noise from an application. No system can be completely immune to power supply noise. Therefore, as an ADC user, designers must be proactive in the power supply design and layout stages. Here are some useful tips to help designers maximize the PCB's immunity to power supply variations:

• Decouple all power rails and bus voltages going to the system board.
• Remember: each increase in gain level will result in an increase of approximately 20 dB per decade.
• If the power leads are long and power specific ICs, devices, and/or areas, they should be decoupled again.
• Decoupling is required for both high and low frequencies.
• A series ferrite bead is often used at the power entry point before the decoupling capacitor to ground. This should be done for every supply voltage entering the system board, whether it comes from an LDO or a switching regulator.
• For added capacitors, use tightly stacked power and ground planes (spacing ≤ 4 mils) so that the PCB design has inherent high-frequency decoupling capabilities.
• As with any good board layout, the power supply should be kept away from sensitive analog circuits, such as the ADC's front-end stage and clock circuits.
• Good circuit segmentation is essential, and some components can be placed on the back side of the PCB to enhance isolation.
• Pay attention to ground return paths, especially on the digital side, to ensure that digital transients do not return to the analog portion of the board. In some cases, a split ground plane may also be helpful.
• Keeping analog and digital reference components on their own planes is a common practice that provides increased isolation from noise and coupling interactions.
• Follow the IC manufacturer's recommendations; if the application note or data sheet doesn't directly address it, research evaluation boards. These are great tools to get started.