A novel current sensing method for switching regulators

As electronic products develop towards miniaturization and portability, monolithic integrated high-efficiency, low-power supply voltage DC-DC converters are widely used. Current detection circuits are used in many power management ICs. In current mode PWM controlled DC-DC converters, the current detection module is an important part of the current loop, which is used to detect the current flowing through the power tube and inductor, and achieve the effect of pulse width modulation by comparing the current detection result with the output of the voltage loop. In voltage mode PWM controlled DC-DC converters, LDO, Charge Pump and other circuits, it can also be used for energy saving and protection purposes such as open circuit, short circuit, overcurrent, etc.

There are three traditional current detection methods:

(1) Use the RDS of the power tube for detection;

(2) Detection using a detection field effect transistor;

(3) Field effect transistor combined with detection resistor.

For switching regulators, this paper proposes a novel current detection method that is different from the traditional current detection method.

1 Traditional current detection method

1.1 Using the RDS of the power tube for detection (RDS SENSING)

When the power tube (MOSFET) is turned on, it works in the variable resistance area and is equivalent to a small resistor. When the MOSFET works in the variable resistance area, the equivalent resistance is:

Where: μ is the channel carrier mobility; Cox is the gate capacitance per unit area; VTH is the turn-on voltage of MOSFET.

As shown in Figure 1, given the equivalent resistance of the MOSFET, the switching current can be detected by detecting the voltage between the drain and source of the MOSFET.

This technology is perfect in theory, it does not introduce any additional power loss, does not affect the efficiency of the chip, and is therefore very practical. However, this technology has a fatal disadvantage of low detection accuracy:

(1) The RDS of MOSFET is inherently nonlinear.

(2) Whether it is the MOSFET inside or outside the chip, its RDS is greatly affected by μ, Cox, and VTH.

(3) The RDS of MOSFET changes exponentially with temperature (the change is 35% from 27 to 100°C).

It can be seen that this detection technology is greatly affected by the process and temperature, and its error is between -50% and +100%. However, because the current detection circuit is simple and does not consume any extra power, it can be used in situations where the current detection accuracy is not high, such as overcurrent protection of DC-DC regulators.

1.2 Using Sense Field Effect Transistor (SENSEFET)

This current detection technology is quite common in practical engineering applications. Its design idea is: as shown in Figure 2, a current detection FET is connected in parallel at both ends of the power MOSFET, and the effective width W of the detection FET is obviously much smaller than that of the power MOSFET. The effective width W of the power MOSFET should be more than 100 times that of the detection FET (assuming that the effective lengths of the two are equal, the same below), so as to ensure that the additional power loss caused by the detection FET is as small as possible. The currents of nodes S and M should be equal to avoid the inaccurate current mirror caused by the FET channel length effect.

When the potentials of nodes S and M are equal, the current IS flowing through the detection FET is 1/N of the power MOSFET current IM (N is the ratio of the width of the power FET to the detection FET), and the value of IS can reflect the size of IM.

1.3 Combination of Detection Field Effect Transistor and Detection Resistor

As shown in Figure 3, this detection technology is an improved form of the previous one, except that its detection device is not FET but a small resistor. In this detection circuit, the resistance value of the small resistor is much more accurate than the RDS of the detection FET, and its detection accuracy is relatively higher. In addition, there is no need for a special circuit to ensure that the voltage at the drain end of the power FET and the detection FET is equal, which reduces the design difficulty. However, the cost is that the additional power loss caused by the detection of the small resistor is smaller than 1/N2 of the first detection technology (N is the ratio of the width of the power FET to the detection FET).

The disadvantage of this technology is that, due to the unequal VDS of M1 and M3 (considering the influence of VDS on IDS), the ratio of IM to IS is not strictly equal to N, but this deviation is relatively small. In engineering, N should be as large as possible and RSENSE should be as small as possible. This detection technology can be used in high-efficiency, low-voltage output, and large-load application environments.

2 New current detection method

In FIG4 , N_DRV is the synchronous tube gate drive signal of the BUCK regulator, N_DRV_DC is the DC component filtered out by N_DRV after passing through a third-order RC low-pass filter, and the DC component is input to one end of the comparator, and the other end of the comparator is input to a reference voltage value BIAS, and the output LA28 (digital signal, output to the control logic of the chip) of the comparator is a DC-DC load current state detection signal.

The functions of the current detection circuit are as follows:

In a voltage regulator chip, there is both a DC-DC (BLYCK) and an LDO. It works in PWM mode under medium and heavy loads, and works in LD0 under light load (about 3 mA or less). The function of the current detection circuit proposed in this article is: when its load current is less than a certain value (at this time the switching regulator is in DCM mode), the LA28 level jumps to realize the mode switching from PWM mode to LD0 mode.

It should be noted that if the output load current is detected directly or by taking the average value of the inductor current, it will bring difficulties in circuit implementation. However, the detection method proposed here does not have this problem.

This architecture diagram is an equivalent diagram of the DC-DC load current state detection circuit. Its function is that when the DC-DC load current is lower than 3 mA, its output signal LA28 changes from high to low, thereby realizing the switch from PWM mode to LD0. Its basic principle is to use the relationship between the load current and the switch gate drive signal N_DRV in DCM mode (when the load current is 3 mA, the DC-DC is in DCM mode), and monitor the change of the output load current by detecting N_DRV, so as to realize the switch from PWM mode to LDO when the load current is lower than 3 mA.