Power over Ethernet (PoE)

The IEEE 802.3af standard for PoE requires that all data terminal equipment (DTE) use the same cable as the data to receive power. The standard specifies the transmission of 48V DC over unshielded twisted pair cables, such as Class 5. This way, no local power supply is required.

What does IEEE 802.3af include?

The IEEE 802.3af standard proposes requirements for using existing cables to provide and receive power, including equipment (PSE) that provides power to the cable, and power receiving devices (PD). This standard defines the interface between PSE and PD, and also involves related detection and classification protocols. The diagram shows a simplified typical PoE system.

How does a PoE system sense when power is needed?

The PD requests power using a sensing method that causes the PSE to find a valid PD. PSE searches for effective PD by sending a 2.8V~10V signal to the power line. An effective PD senses this voltage and adds a 23.75kΩ~26.25kΩ resistor on the power line. Once the PSE senses the generated current, it assumes that there is a valid PD requesting power.

How does the PD behave if it cannot receive power?

If the PD receives no power, it adds a resistor with a value higher or lower than listed for a valid PD. At the low end, 12kΩ~23.75kΩ means that the PD does not require power supply. At the high end, the range is between 26.25kΩ~45kΩ. The PSE considers anything below 12 kΩ and above 45 kΩ to be an invalid PD detection signature.

What are the power and current limits for PoE systems?

The maximum current received by a single node is 350mA. To allow for some allowance for cable-related power losses, the total continuous power received by each node is 12.95 W.

How does the PSE determine the necessary power requirements?

After the sensing session is completed, the PSE can generate a PD classification at will. The PSE uses PD classification to determine the maximum power required for normal operation of the PD. The IEEE 802.3af standard defines 5 different classification standards, including minimum and maximum power and voltage.

How does PSE determine classification?

PSE is implemented by increasing the voltage on the power line to between 15.5V and 20.5V. Classification is determined by the amount of current drawn by the PD.

What’s next for PSE?

After completing the sensing and optional classification stages, the PSE ramps its output voltage up to 42V. Once the low voltage cut-off (UVLO) release threshold is reached, an internal FET turns on and the PD begins normal operation. This remains true as long as the input voltage remains above the UVLO threshold. For most PDs, a board-level DC-DC converter downconverts the input voltage to produce the required voltage.

How to choose capacitor value?

According to the IEEE 802.3af specification, the PSE must limit the inrush current if the input capacitance is less than 180 μF. When the input capacitance is greater than 180μF, the PD is required to limit the surge current to less than 400 mA. The input capacitance of PD to PSE must also be between 0.05μF~0.12μF.

How does PoE handle voltage transients?

Using long cables and transformers can produce transient changes greater than 68V. To prevent these transients from exceeding the application's maximum voltage, designers can add a transient voltage surge suppressor (TVS) or similar Zener device between the positive and negative supplies.

What are the requirements for transient suppression?

Adding bypass capacitors in parallel with the TVS helps protect the PoE system from damage caused by transients. Select the TVS so that it starts at greater than the 57V maximum application voltage and before reaching the 68V maximum absolute rating.

How do designers configure PoE systems?

ICs from multiple manufacturers simplify PoE system design. These ICs typically include an IEEE 802.3af compliant PD and DC-DC converter interface.

Which system units provide fault protection?

First, the PSE may remove power supplies from PDs that do not meet their power supply classification or that have a maximum sink current of 400 mA. Secondly, the PD interface chip may have both internal current and thermal current limiting protection. Finally, the selected power controller may also have cycling current limit protection. Different chips have different levels of protection.